IP Library Granted Patent US 8,812,415
Granted Patent B2
US 8,812,415 · App. 13/931,676 · Granted Aug 19, 2014

Neuromorphic and synaptronic spiking neural network crossbar circuits with synaptic weights learned using a one-to-one correspondence with a simulation

Inventor: Dharmendra S. Modha (San Jose, CA)
Assignee: International Business Machines Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,812,415
App. No.
13/931,676
Granted
Aug 19, 2014
Kind
B2
Abstract

Embodiments of the invention provide neuromorphic-synaptronic systems, including neuromorphic-synaptronic circuit chips implementing spiking neural network with synaptic weights learned using simulation. One embodiment includes simulating a spiking neural network to generate synaptic weights learned via the simulation while maintaining one-to-one correspondence between the simulation and a digital circuit chip. The learned synaptic weights are loaded into the digital circuit chip implementing a spiking neural network, the digital circuit chip comprising a neuromorphic-synaptronic spiking neural network including plural synapse devices interconnecting multiple digital neurons.

Claims (67)

1. A neuromorphic-synaptronic neural network, comprising:

multiple neuromorphic-synaptronic circuits, wherein each circuit comprises a crossbar including a plurality of synapse devices interconnecting multiple digital electronic neurons with multiple digital electronic axons;

an interconnect network for interconnecting said multiple circuits, wherein each

crossbar of each circuit is intertwined with at least one other crossbar of at least one other circuit via the interconnect network;

an interface unit configured for programming said multiple circuits with information relating to synaptic connectivity, neuron parameters, and connectivity between said multiple circuits; and

a soma module, wherein the soma module is configured for integrating synaptic inputs received by a neuron, and controlling generation of output for said neuron

wherein said multiple circuits operate deterministically;

wherein said multiple circuits maintain a one-to-one correspondence with a simulation;

wherein said multiple circuits are programmed with simulation information including synaptic weights, neuron parameters, and connectivity data relating to connectivity between said multiple circuits; and

wherein said simulation information is learned during said simulation.

2. The network of claim 1 , further comprising:

an address event representation (AER) module configured for facilitating

communication between said multiple circuits.

3. The network of claim 1 , wherein programming said multiple circuits with information relating to synaptic connectivity, neuron parameters, and connectivity between said multiple circuits comprises:

programming each circuit with synaptic weights for synapse devices of said circuit;

programming each circuit with neuron parameters for neurons of said circuit; and

programming said multiple circuits with connectivity data specifying at least one

interconnection between said multiple circuits, wherein each interconnection is between a neuron of a circuit and an axon of either the same circuit or another circuit.

4. The network of claim 1 , wherein:

said network operates deterministically; and

said network maintains one-to-one correspondence with a simulation.

5. The network of claim 4 , wherein the interface unit is further configured for programming said multiple circuits with simulation information including synaptic weights, neuron parameters, and connectivity data relating to connectivity between said multiple circuits.

6. The network of claim 5 , wherein said simulation information is learned during said simulation.

7. The network of claim 1 , wherein the interconnect network is event-driven.

8. The network of claim 1 , wherein:

said multiple circuits are arranged in a two-dimensional grid pattern; and

the interconnect network is a cross-quilt interconnect network where crossbars of

said multiple circuits are intertwined.

9. The network of claim 8 , wherein each circuit is configured to communicate with one or more of the following:

a first physically adjacent circuit positioned directly above said circuit;

a second physically adjacent circuit positioned directly below said circuit;

a third physically adjacent circuit positioned directly left of said circuit; and

a fourth physically adjacent circuit positioned directly right of said circuit.

10. The network of claim 1 , wherein:

said multiple circuits are arranged in a three-dimensional grid pattern; and

the interconnect network is a cross-quilt interconnect network where crossbars of

said multiple circuits are intertwined.

11. The network of claim 10 , wherein each circuit is configured to communicate with one or more of the following:

a first physically adjacent circuit positioned directly above said circuit and within a two-dimensional plane that includes said circuit;

a second physically adjacent circuit positioned directly below said circuit and within said two-dimensional plane;

a third physically adjacent circuit positioned directly right of said circuit and within said two-dimensional plane;

a fourth physically adjacent circuit positioned directly left of said circuit and within said the two-dimensional plane;

a fifth physically adjacent circuit positioned in a top plane that is parallel and directly above said two-dimensional plane; and

a sixth physically adjacent circuit positioned in a bottom plane that is parallel and directly below said two-dimensional plane.

12. The network of claim 1 , wherein each circuit is configured to communicate with another circuit that is not physically adjacent to said circuit via a sequence of hops.

13. The network of claim 1 , wherein:

axons of at least one circuit are configured to receive inputs from one or more external sensors; and

neurons of at least one circuit are configured to send outputs to one or more external actuators.

14. The network of claim 4 , wherein maintaining one-to-one correspondence with said simulation includes programming neurons of at least one circuit with information relating to randomness for at least one of synaptic yield and axonal delay.

15. The network of claim 4 , wherein each axon has a corresponding delay buffer that facilitates said network operating deterministically and maintaining one-to-one correspondence with said simulation.

16. The network of claim 4 , wherein maintaining one-to-one correspondence with said simulation includes factoring into said simulation synaptic yield and one or more hardware failures associated with said network.

17. A method, comprising:

interconnecting multiple neuromorphic-synaptronic circuits, wherein each

circuit comprises a crossbar including a plurality of synapse devices interconnecting multiple digital electronic neurons with multiple digital electronic axons;

operating said multiple circuits deterministically;

maintaining a one-to-one correspondence with a simulation;

programming said multiple circuits with simulation information relating to

synaptic connectivity including synaptic weights, neuron parameters, and connectivity data relating to connectivity between said multiple circuits, wherein said simulation information is learned during said simulation; and

for at least one neuron, integrating synaptic inputs received by said neuron, and controlling generation of output for said neuron;

wherein each crossbar of each circuit is intertwined with at least one other crossbar of at least one other circuit.

18. A non-transitory computer program product for a neuromorphic-synaptronic neural network comprising multiple interconnected neuromorphic-synaptronic circuits, wherein each circuit comprises a crossbar including a plurality of synapse devices interconnecting multiple digital electronic neurons with multiple digital electronic axons, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:

operate said multiple circuits deterministically;

maintain a one-to-one correspondence with a simulation;

program said multiple circuits with simulation information relating to synaptic

connectivity including synaptic weights, neuron parameters, and connectivity data relating to connectivity between said multiple circuits, wherein said simulation information is learned during said simulation; and

for at least one neuron, integrating synaptic inputs received by said neuron, and controlling generation of output for said neuron;

wherein each crossbar of each circuit is intertwined with at least one other crossbar of at least one other circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2013
From: MODHA, DHARMENDRA S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030715/0338 →
Continuity (2)
Continuation 12916332 · Oct 29, 2010
Related Publication 20140188771A1 · Jul 3, 2014