Method of merging blocks in a semiconductor memory device, and semiconductor memory device to perform a method of merging blocks

1. A method of merging blocks in a semiconductor memory device, the method comprising:

writing a plurality of data into one or more first blocks using a first program method;

selecting one or more merge target blocks that are required to be merged among the one or more first blocks;

selecting a merge-performing block for a block merge operation among the one or more first blocks and one or more second blocks;

writing a plurality of merge target data from the merge target blocks into the merge-performing block using a second program method that is different from the first program method; and

selecting between the first program method and the second program method by changing one or more program parameters.

2. The method of claim 1 , further comprising:

erasing the plurality of merge target data from the merge target blocks.

3. The method of claim 2 , wherein the semiconductor memory device corresponds to a NAND flash memory device including a plurality of single level memory cells or a plurality of multi level memory cells.

4. The method of claim 3 , wherein:

the plurality of data and the plurality of merge target data are written on a page basis, and

the plurality of data and the plurality of merge target data are erased on a block basis.

5. The method of claim 1 , wherein program parameters of the first program method are different from program parameters of the second program method.

6. The method of claim 1 , wherein:

the first program method corresponds to a shadow program method, and

the second program method corresponds to a reprogram method.

7. The method of claim 6 , wherein the plurality of merge target data are written from the merge target blocks into the merge-performing block via a page buffer unit.

8. The method of claim 1 , wherein:

the first program method corresponds to an on-chip buffered program method using a first incremental step pulse, and

the second program method corresponds to the on-chip buffered program method using a second incremental step pulse.

9. The method of claim 8 , wherein the plurality of merge target data are written from the merge target blocks to the merge-performing block via a page buffer unit and a single level memory cell block.

10. The method of claim 8 , wherein the first incremental step pulse has a voltage level lower than that of the second incremental step pulse.

11. A method of merging blocks in a semiconductor memory device, the method comprising:

loading an external data from an external device into a buffer unit;

writing the external data from the buffer unit into a merge target block as a merge target data using a first program method, the merge target block being a single level memory cell block;

loading the merge target data from the merge target block into the buffer unit; and

writing the merge target data from the buffer unit into a merge-performing block using a second program method different from the first program method, the merge-performing block being a multi level memory cell block,

wherein the first program method uses a first incremental step pulse and the second program method uses a second incremental step pulse, and

wherein the first incremental step pulse and the second incremental step pulse have different voltage levels.

12. The method of claim 11 , wherein the merge target block operates at a higher speed and has a lower cell density than the merge-performing block.

13. The method of claim 11 , wherein the first program method and the second program method have different parameters, the parameters including at least one of incremental step pulse program (ISPP) conditions, verify/read levels, and sensing schemes.

14. The method of claim 6 , wherein the shadow program method is configured to perform a least significant bit program that programs the memory cells to have one of previous threshold voltage states corresponding to N bits, and to perform a most significant bit program that programs the memory cells to have one of final threshold voltage states corresponding to N+1 bits.

15. The method of claim 6 , wherein the reprogram method is configured to perform a pre-program that programs the memory cells to have coarse threshold voltage distributions, and to perform a reprogram that programs the memory cells to have fine threshold voltage distributions that are narrower than the coarse threshold voltage distributions.

16. A semiconductor memory device, comprising:

a memory cell array including a merge target block and a merge-performing block, the merge target block being a single level memory cell block, and the merge-performing block being a multi-level cell block;

a page buffer unit; and

a program controller configured to control the page buffer unit to load an external data from an external device, to control the page buffer unit to write the loaded external data into the merge target block as a merge target data using a first program method, to control the page buffer unit to the merge target data from the merge target block, to control the page buffer unit to write the loaded merge target data into the merge-performing block using a second program method different from the first program method, and to select between the first program method and the second program method by changing one or more program parameters.

17. The semiconductor memory device of claim 16 , wherein the first program method uses a first incremental step pulse and the second program method uses a second incremental step pulse.

18. The semiconductor memory device of claim 17 , wherein the first incremental step pulse and the second incremental step pulse have different voltage levels.

19. The semiconductor memory device of claim 16 , wherein the one or more program parameters include incremental step pulse program conditions, verify/read levels, and sensing schemes.