Router and many-core system
According to one embodiment, a router manages routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access. The router includes an analyzer, a packet memory and a controller. The analyzer determines whether the packet is a read-packet or a write-packet. The packet memory stores at least part of the write-packet issued by one of the cores. The controller stores cache data of the write-packet and a cache address in the packet memory when the analyzer determines that the packet is the write-packet. The cache address indicates an address in which the cache data is stored. The controller outputs the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory.
1. A router configured to manage routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access, the router comprising:
an analyzer configured to determine whether the packet is a read-packet or a write-packet;
a packet memory configured to store at least part of the write-packet issued by one of the cores; and
a controller configured to,
when the analyzer determines that the packet is the write-packet and the packet memory is not full, store cache data of the write-packet and a cache address in the packet memory, the cache address indicating an address in which the cache data is stored,
when the analyzer determines that the packet is the write-packet and the packet memory is full, output the packet to a subsequent router or one of the cache memories without storing the packet in the packet memory, and
when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory, output the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet.
2. The router of claim 1 , wherein the controller stores unique information of the core issuing the write packet.
3. The router of claim 1 , wherein the controller outputs read-packet to the cache memory or another router when the cache address is not stored in the packet memory, the cache memory or another router corresponding to the cache address in the read-packet.
4. The router of claim 1 , further comprising:
a read-input port configured to input the read-packet;
a write-input port configured to input the write-packet;
a read-output port configured to output the read-packet;
a write-output port configured to output the write-packet; and
a buffer configured to store the read-packet inputted by the read-input port and the write-packet inputted by the write-input port,
wherein the controller stores at least part of the write-packet stored in the buffer to the packet memory when the analyzer determines that packet is the write-packet.
5. A router configured to manage routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access, the router comprising:
an analyzer configured to determine whether the packet is a read-packet or a write-packet;
a packet memory configured to store at least part of the write-packet issued by one of the cores; and
a controller configured to store cache data of the write-packet and a cache address in the packet memory when the analyzer determines that the packet is the write-packet, the cache address indicating an address in which the cache data is stored, and output the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory,
wherein the controller sets a replace bit to a replace area in the packet memory, the replace bit indicating whether the cache data stored in the packet memory can be read and deleted or not.
6. The router of claim 5 , wherein the controller sets the replace bit to the replace area when reading of the write-packet is ended, the replace bit permitting the cache data to be read and deleted.
7. The router of claim 6 , wherein the controller sets the replace bit to the replace area when the cache data stored in the packet memory is outputted as the response data, the replace bit permitting the cache data to be read and prohibiting the cache data to be deleted.
8. The router of claim 6 , wherein the controller stores unique information of the core issuing the write packet.
9. The router of claim 5 , wherein the controller sets the replace bit to the replace area when the cache data stored in the packet memory is outputted as the response data, the replace bit permitting the cache data to be read and prohibiting the cache data to be deleted.
10. The router of claim 5 , wherein the controller stores unique information of the core issuing the write packet.
11. A many-core system comprising:
a plurality of cores;
at least one of cache memories to which the cores can access;
an analyzer configured to determine whether the packet is a read-packet or a write-packet;
a packet memory configured to store at least part of the write-packet issued by one of the cores; and
a controller configured to,
when the analyzer determines that the packet is the write-packet and the packet memory is not full, store cache data of the write-packet and a cache address in the packet memory, the cache address indicating an address in which the cache data is stored,
when the analyzer determines that the packet is the write-packet and the packet memory is full, output the packet to a subsequent router or one of the cache memories without storing the packet in the packet memory, and
when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory, output the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet.
12. The system of claim 11 , wherein the controller stores unique information of the core issuing the write packet.
13. The system of claim 11 , wherein the controller outputs read-packet to the cache memory or another router when the cache address is not stored in the packet memory, the cache memory or another router corresponding to the cache address in the read-packet.
14. The system of claim 11 , further comprising:
a read-input port configured to input the read-packet;
a write-input port configured to input the write-packet;
a read-output port configured to output the read-packet;
a write-output port configured to output the write-packet; and
a buffer configured to store the read-packet inputted by the read-input port and the write-packet inputted by the write-input port,
wherein the controller stores at least part of the write-packet stored in the buffer to the packet memory when the analyzer determines that packet is the write-packet.
15. A many-core system comprising:
a plurality of cores;
at least one of cache memories to which the cores can access;
an analyzer configured to determine whether the packet is a read-packet or a write-packet;
a packet memory configured to store at least part of the write-packet issued by one of the cores; and
a controller configured to store cache data of the write-packet and a cache address in the packet memory when the analyzer determines that the packet is the write-packet, the cache address indicating an address in which the cache data is stored, and output the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory,
wherein the controller sets a replace bit to a replace area in the packet memory, the replace bit indicating whether the cache data stored in the packet memory can be read and deleted or not.
16. The system of claim 15 , wherein the controller sets the replace bit to the replace area when reading of the write-packet is ended, the replace bit permitting the cache data to be read and deleted.
17. The system of claim 16 , wherein the controller sets the replace bit to the replace area when the cache data stored in the packet memory is outputted as the response data, the replace bit permitting the cache data to be read and prohibitting the cache data to be deleted.
18. The system of claim 16 , wherein the controller stores unique information of the core issuing the write packet.
19. The system of claim 15 , wherein the controller sets the replace bit to the replace area when the cache data stored in the packet memory is outputted as the response data, the replace bit permitting the cache data to be read and prohibitting the cache data to be deleted.
20. The system of claim 15 , wherein the controller stores unique information of the core issuing the write packet.