Time-to-digital converter for a medical imaging system
A timing circuit that includes a first serializer/deserializer (SERDES) configured to receive a parallel rate clock signal and a system clock start signal from an imaging system and generate a first output, a second SERDES configured to receive a stop signal that is based on an output from the medical imaging system and generate a second output, and a timestamp calculator configured to utilize the first and second outputs to generate a timestamp. A medical imaging system and a method of operating a timing circuit are also described.
1. A timing circuit comprising:
a first serializer/deserializer (SERDES) configured to receive a parallel rate clock signal and a system clock start signal from an imaging system and generate a first output based on the system clock start signal;
a second SERDES configured to receive the parallel rate clock signal and a stop signal that is based on an output from the imaging system and generate a second output based on the output from the imaging system; and
a timestamp calculator configured to compare the first output from the first SERDES based on the system clock signal and the second output from the second SERDES based on the output from the medical imaging system to generate a timestamp.
2. The timing circuit of claim 1 , further comprising:
a first leading edge detector configured to receive the first output and determine at least one least significant bit of the system clock start signal; and
a second leading edge detector configured to receive the second output and determine at least one least significant bit of the stop signal.
3. The timing circuit of claim 2 , further comprising a parallel clock counter configured to determine at least one most significant bit of the stop signal, the timestamp calculator configured to utilize the least significant bits of the system clock start signal, the least significant bits of the stop signal, and the most significant bits of the stop signal to generate the timestamp, wherein the timestamp is generated by subtracting a first value from a second value, the first value including the most significant bits of the stop signal and the least significant bits of the stop signal, the second value including the most significant bits of the start signal and the least significant bits of the start signal.
4. The timing circuit of claim 1 , wherein the first SERDES and the second SERDES comprises single input parallel output shift registers programmed on a field programmable gate array.
5. The timing circuit of claim 1 , wherein the imaging system includes a positron emission tomography (PET) detector assembly, the timestamp indicating a time that a gamma ray is detected at the PET detector assembly, the stop signal corresponding to a triggering signal corresponding to the detection of the gamma ray at the PET detector assembly.
6. A method of operating an imaging system that includes a field programmable gate array, said method comprising:
receiving at a first serializer/deserializer (SERDES) receive circuit a parallel-rate clock and a time-to-digital (TDC) start signal, and generating a first parallel word that represents a leading edge position of the TDC start signal using the first SERDES receive circuit;
receiving at a second SERDES receive circuit the parallel-rate clock and a TDC stop signal and generating a second parallel word that represents a leading edge position of the TDC stop signal using the second SERDES receive circuit, the TDC stop signal based on an output of the imaging system;
receiving the parallel-rate clock and the TDC start signal at a first leading edge detection circuit and generating a TDC start edge found signal and an encoded value representing a 0 to 1 transition or 1 to 0 transition bit position in the TDC start signal;
receiving the parallel-rate clock and the TDC stop signal at a second leading edge detection circuit and generating a TDC stop edge found signal and an encoded value representing a 0 to 1 transition or 1 to 0 transition bit position in the TDC stop signal;
receiving the parallel-rate clock and the TDC start edge found signal at a first binary counter circuit, and generating a binary count representing a number of parallel-rate clock cycles between the TDC start signal and the TDC start edge found signal to generate a TDC start signal conversion;
receiving the parallel-rate clock and the TDC stop edge found signal at a second binary counter circuit and generating a binary count representing a number of parallel-rate clock cycles between the TDC stop signal and the TDC stop edge found signal to generate a TDC stop signal conversion; and
subtracting the TDC stop signal conversion from the TDC start signal conversion to generate a timestamp.
7. The method of claim 6 , wherein a plurality of TDC stop conversion circuits are selected and an electronic skew between the TDC stop conversion circuits is measured during a calibration and a correction is applied during subsequent TDC stop signal conversions.
8. The method of claim 6 , wherein the parallel-rate input clock's frequency is re-configurable during operation and the frequency is selected to scale the precision of TDC conversion.
9. The method of claim 6 , wherein a SERDES circuit serial-to-parallel deserialization factor is re-configurable during operation and the deserialization factor is selected to scale the precision of the TDC conversion.
10. The method of claim 6 , wherein a SERDES circuit electronic input type is selectable, and the SERDES circuit electronic input type is selected to match an electronic output type of a circuit generating the TDC start signal and the TDC stop signal.
11. The method of claim 6 , wherein a SERDES circuit electronic input threshold level is selectable or re-configurable during operation and the threshold level is selected to match an electronic output level of a circuit generating the TDC start signal and the TDC stop signal.
12. The method of claim 6 , wherein a SERDES circuit electronic input signal conditioning is selectable during design or re-configurable during operation and is selected to match an electronic output signal of a circuit generating the TDC start signal and the TDC stop signal.
13. The method of claim 6 , wherein the parallel-rate input clock is divided into N-phases, where each clock is 360/N out-of-phase with a nearest neighbor clock.
14. The method of claim 13 , wherein the SERDES receive circuits, the leading-edge detection circuits, and the binary counter circuits are duplicated for each of the N-phases of the parallel-rate input clock.
15. The method of claim 14 , wherein for each phase of the parallel-rate clock, there is a corresponding TDC start conversion and stop conversion, with each conversion circuit receiving a single, unique phase of the parallel-rate clock.
16. An imaging system comprising:
a plurality of detectors supported by a gantry;
a plurality of acquisition circuits coupled to the detectors, wherein the acquisition circuits provide event detection signals; and
a field programmable gate array (FPGA) utilized to timestamp the event detection signals, said field programmable gate array programmed to include:
a first serializer/deserializer (SERDES) configured to receive a parallel rate clock signal and a system clock start signal from the imaging system and generate a first output based on the system clock start signal;
a second SERDES configured to receive the parallel rate clock signal and a stop signal that is based on an output from the imaging system and generate a second output based on the output from the imaging system; and
a timestamp calculator configured to compare the first output from the first SERDES based on the system clock signal and the second output from the second SERDES based on the output from the medical imaging system to generate a timestamp.
17. The imaging system of claim 16 , wherein the FPGA further comprises:
a first leading edge detector configured to receive the first output and determine at least one least significant bit of the system clock start signal; and
a second leading edge detector configured to receive the second output and determine at least one least significant bit of the stop signal.
18. The imaging system of claim 16 , wherein the FPGA further comprises a parallel clock counter configured to determine at least one most significant bits of the stop signal, the timestamp calculator configured to utilize the least significant bits of the system clock start signal, the least significant bits of the stop signal, the most significant bits of the system clock start signal, and the most significant bits of the stop signal to generate the timestamp, wherein the timestamp is generated by subtracting a first value from a second value, the first value including the most significant bits of the stop signal and the least significant bits of the stop signal, the second value including the most significant bits of the start signal and the least significant bits of the start signal.
19. The imaging system of claim 16 , wherein the imaging system includes a positron emission tomography (PET) detector assembly, the timestamp indicating a time that a gamma ray is detected at the PET detector assembly, the stop signal corresponding to a triggering signal corresponding to the detection of the gamma ray at the PET detector assembly.