IP Library › Granted Patent US 8,824,492
Granted Patent B2
US 8,824,492 · App. 13/117,821 · Granted Sep 2, 2014

Accelerator system for remote data storage

Inventors: Michael H. Wang (Hillsborough, CA); Steven Mark Casselman (Santa Clara, CA); Babu Rao Kandimalla (San Jose, CA); Stephen Paul Sample (Saratoga, CA); Lawrence A. Laurich (Sunnyvale, CA)
Assignee: DRC Computer Corporation
G06F3/0619G06F3/067G06F21/78H04L63/20H04L63/08H04L67/1097H04L63/0428H04L69/12H04L69/14G06F3/0646G06F21/72G06F21/602G06F2221/2107H04L67/06G06F21/85
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Quick Facts
Patent No.
US 8,824,492
App. No.
13/117,821
Granted
Sep 2, 2014
Kind
B2
Abstract

Data processing and an accelerator system therefor are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Claims (45)

1. A data processing system, comprising:

a bus;

an accelerator coupled to the bus;

the accelerator having an application function block the application function block to process data to provide processed data to storage;

a network interface coupled to obtain the processed data from the storage for transmission;

a switch coupled between the bus and the accelerator and between the accelerator and the network interface;

memory accessible by the application function block via the accelerator;

wherein the bus is a host system-side peripheral interconnect bus;

wherein the switch provides the data to and from the peripheral interconnect bus and the accelerator; and

wherein the switch provides the processed data to and from the memory and the network interface.

2. The data processing system according to claim 1 , wherein the application function block is further for processing of the processed data to restore the data.

3. The data processing system according to claim 1 , wherein:

the switch is configured to control peer-to-peer routing between the accelerator and the network interface for retrieval of the processed data from the memory by the network interface; and

the switch is further configured to control peer-to-peer routing between the network interface and the accelerator for storage of the processed data in the memory by the network interface.

4. The data processing system according to claim 3 , wherein the accelerator includes a Programmable Logic Device (“PLD”) having the application function block instantiated in whole or in part in programmable logic resources of the PLD.

5. The data processing system according to claim 1 , further comprising at least one transmitter or transceiver coupled to the network interface for transmitting the processed data.

6. A host system, coupled to the data processing system according to claim 5 , for providing commands and the data to the switch via the peripheral interconnect bus.

7. The host system according to claim 6 , wherein the network interface is coupled to a network for storage of the processed data in at least one storage device remotely located from the host system.

8. The host system according to claim 6 , wherein:

the network interface is coupled to receive a first subset of the commands;

the network interface is configured to use the first subset of the commands to read the processed data from the memory; and

the network interface obtains the processed data read from the memory via a data-only path.

9. The host system according to claim 8 , wherein:

the network interface is coupled to receive the first subset of the commands via a command-only path; and

the accelerator is coupled to receive a second subset of the commands and the data via a data and command path.

10. The host system according to claim 6 , wherein:

the processed data does not pass to the network interface via the peripheral interconnect bus.

11. The host system according to claim 6 , wherein the peripheral interconnect bus is a Peripheral Component Interconnect Express (“PCIe”) bus.

12. The host system according to claim 6 , wherein the network interface includes a direct memory access controller to read and write the processed data from and to the memory.

13. The host system according to claim 6 , wherein the memory is externally coupled to the accelerator.

14. A method for processing data, comprising:

providing a command and a payload pointer to an accelerator system;

obtaining, by the accelerator system, data responsive to the payload pointer;

processing the data by the accelerator system responsive to the command to provide processed data;

storing the processed data locally in memory of the accelerator system;

initiating a memory access by a network interface of the accelerator system;

obtaining the processed data from the memory responsive to the memory access; and

transmitting the processed data obtained by the network interface to cloud storage;

wherein:

the memory access is a direct memory access;

the direct memory access and the processed data obtained in response thereto are routed peer-to-peer by a switch coupling the network interface and Programmable Logic Device (“PLD”) to one another; and

the memory is coupled to the PLD.

15. The method according to claim 14 , further comprising:

receiving the processed data from the cloud storage to the network interface; and

storing the processed data in the memory for subsequent processing by the PLD.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2011
From: KANDIMALLA, BABU RAO
To: DRC COMPUTER CORPORATION
Reel/Frame 026651/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2011
From: WANG, MICHAEL H.; CASSELMAN, STEVEN MARK; SAMPLE, STEPHEN PAUL; LAURICH, LAWRENCE A.
To: DRC COMPUTER CORPORATION
Reel/Frame 026357/0886 →
Continuity (2)
Provisional Application 61349560 · May 28, 2010
Related Publication 20110295967A1 · Dec 1, 2011