Non-volatile memory device having three dimensional, vertical channel, alternately stacked gate electrode structure
A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.
1. A non-volatile memory device comprising:
a plurality of memory cells stacked along a channel vertically protruding from a substrate;
a well region arranged in the substrate;
a common source region arranged within the well region; and
a pickup region arranged in the substrate to connect the channel to the well region,
wherein a conductive-type of the well region is the same as that of the pickup region and the channel, and the conductive-type of the well region is different from that of the common source region.
2. The non-volatile memory device of claim 1 , wherein the plurality of memory cells are configured to operate in an enhancement-mode.
3. The non-volatile memory device of claim 1 , wherein a width of the pickup region is smaller than a width of the channel.
4. The non-volatile memory device of claim 1 , wherein the channel is electrically connected to the well region through the pickup region.
5. The non-volatile memory device of claim 1 , wherein the plurality of memory cells include:
a plurality of inter-layer dielectric layers and a plurality of gate electrodes alternately stacked over a substrate;
a plurality of channels passing through the plurality of inter-layer dielectric layers and the plurality of gate electrodes and protruding from the substrate; and
a plurality of junction layers disposed between the plurality of channels and the plurality of inter-layer dielectric layers.
6. The non-volatile memory device of claim 5 , further comprising:
a charge blocking layer, a charge trap layer, and a tunnel insulation layer disposed between the plurality of channels and the plurality of gate electrodes.
7. The non-volatile memory device of claim 5 , wherein the plurality of channels are doped with a P-type impurity, and the plurality of junction layers are doped with an N-type impurity.
8. The non-volatile memory device of claim 7 , wherein a doping concentration of the N-type impurity is in a range of from approximately 1E10/cm 2 to approximately 1E15/cm 2 .