Semiconductor device and method of manufacturing the same
In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
1. A semiconductor memory device, comprising:
a plurality of control gates stacked in first and second regions region of a substrate;
a plurality of interlayer insulating layers stacked in a portion of the second region of the substrate, each interlayer insulating layer formed at the same level as a corresponding one of the control gates;
a plurality of sub-control gates stacked in the first and second regions of the substrate and interposed between the control gates and the interlayer insulating layers; and
a common node penetrating the interlayer insulating layers and the sub-control gates.
2. The semiconductor memory device of claim 1 , further comprising:
a channel layer positioned in the first region of the substrate and penetrating the control gates; and
charge storage layers surrounding the channel layer and interposed between the channel layer and the control gates.
3. The semiconductor memory device of claim 1 , wherein the sub-control gates and the control gates formed in the second region are stepwise patterned.
4. The semiconductor memory device of claim 3 , further comprising:
contact plugs coupled to the stepwise patterned control gates, respectively, in the second region.
5. The semiconductor memory device of claim 1 , further comprising:
at least one lower selection gate formed under the control gates; and
at least one upper selection gate formed above the control gates.
6. The semiconductor memory device of claim 5 , wherein at least one of the control gates adjacent to the lower selection gate or the upper selection gate belongs to a dummy cell.
7. The semiconductor memory device of claim 1 , wherein the common node is configured to apply a common voltage to the sub-control gates during a program, read, or erase operation.
8. The semiconductor memory device of claim 1 , wherein the common node is positioned in the second region.
9. The semiconductor memory device of claim 1 , wherein the sub-control gates are electrically insulated from the control gates.
10. The semiconductor memory device of claim 1 , further comprising:
memory cells stacked in the first region and corresponding to the control gates,
wherein the second region is free of memory cells.
11. The semiconductor memory device of claim 10 , further comprising:
at least one slit in the first region between adjacent stacks of memory cells, the slit penetrating the control gates and being filled with an insulating material.