IP Library Granted Patent US 8,832,361
Granted Patent B2
US 8,832,361 · App. 13/962,455 · Granted Sep 9, 2014

Storage device including flash memory and capable of predicting storage device performance based on performance parameters

Inventor: Akihisa Fujimoto (Tokyo, JP)
Assignee: Kabushiki Kaisha Toshiba
G06F12/0246G11C16/20G06F3/0679G06F13/385G06F3/061G06F3/0632
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Quick Facts
Patent No.
US 8,832,361
App. No.
13/962,455
Granted
Sep 9, 2014
Kind
B2
Abstract

A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Claims (27)

1. A storage device comprising:

a semiconductor memory which has memory areas, a part of the memory areas being assigned to a user area which can be accessed from outside, the user area including allocation units (AUs), each management unit including recording units (RUs);

a controller instructing to write data to the semiconductor memory in accordance with a request the controller receives;

a first register provided in the controller and holding a class value corresponding to a performance class of the storage device; and

a second register provided in the controller and holding information of a size of an AU, the size of the AU being memory management information used to manage the user area, wherein

a worst average write performance of the storage device, which is an average of measured sequential writes performance, is larger than or equal to performance specified by the class value held in the first register,

a write size of each of the sequential writes is a size of one of the RUs, and

the first and second registers are accessible from outside.

2. The device according to claim 1 , wherein the second register further holds information on performance of internal data move by the storage device.

3. The device according to claim 1 , wherein the storage device is configured to maintain average write performance larger than or equal to the performance determined by the performance class even with a file information update inserted during writes to RUs.

4. The device according to claim 1 , further comprising:

a cover covering the semiconductor memory and the controller; and

a display portion provided on the cover and displaying the performance class.

5. A storage device comprising:

a semiconductor memory which has memory areas, a part of the memory areas being assigned to a user area which can be accessed from outside, the user area including allocation units (AUs), each management unit including recording units (RUs);

a clock input terminal to receive a clock having a frequency, performance of a bus of the storage device depending on the frequency;

a controller instructing to write data to the semiconductor memory in accordance with a request the controller receives;

a first register provided in the controller and holding a class values value corresponding to a performance class of the storage device related to the frequency of the clock;

a second register provided in the controller and holding information of a size of an AU, the size of the AU being memory management information used to manage the user area, wherein

a worst average write performance of the storage device, which is an average of measured sequential writes performance, is larger than or equal to performance specified by the class value held in the first register,

a write size of each of the sequential writes is a size of one of the RUs and

the first and second registers are accessible from outside.

6. The device according to claim 5 , wherein the second register further holds information on performance of internal data move by the storage device.

7. The device according to claim 5 , wherein the storage device is configured to maintain average write performance larger than or equal to the performance determined by the performance class even with a file information update inserted during writes to RUs.

8. The device according to claim 5 , further comprising:

a cover covering the semiconductor memory and the controller; and

a display portion provided on the cover and displaying the performance class.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
Priority Claims (2)
JP 2004-204028 · Jul 12, 2004 · national
JP 2004-342275 · Nov 26, 2004 · national
Continuity (4)
Continuation 13096731 · Apr 28, 2011
Division 11557120 · Nov 7, 2006
Continuation PCTJP2005013104 · Jul 8, 2005
Related Publication 20130326129A1 · Dec 5, 2013