IP Library › Granted Patent US 8,832,470
Granted Patent B2
US 8,832,470 · App. 13/216,392 · Granted Sep 9, 2014

Powering universal serial bus systems

Inventors: Brian K. Mueller (Fort Collins, CO); Ricky F. Bitting (Fort Collins, CO)
Assignee: LSI Corporation
G06F1/266G05F1/56
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Quick Facts
Patent No.
US 8,832,470
App. No.
13/216,392
Granted
Sep 9, 2014
Kind
B2
Abstract

Described embodiments provide for a regulated voltage supply to a Universal Serial Bus (USB) system. The regulator comprises a pass device that might be coupled to a host device providing a bus voltage. An integrated USB physical layer (PHY) is coupled to the pass device through a control voltage signal pin. A regulation circuit is coupled to the integrated USB PHY, and the regulation circuit supplies about 3.3V from the bus voltage.

Claims (35)

1. A regulation apparatus, comprising:

a pass device adapted to receive a bus voltage from a host device;

an integrated USB physical layer (PHY) coupled to the pass device through a control voltage signal pin; and

a regulation circuit coupled to the integrated USB PHY and adapted to supply substantially 3.3 volts (V) from the bus voltage.

2. The regulation apparatus of claim 1 , wherein the regulation circuit is comprised 1.8V input/output (I/O) devices.

3. The regulation apparatus of claim 1 , wherein the regulation circuit and the integrated USB PHY are co-located on a system on chip (SoC).

4. The regulation apparatus of claim 1 , wherein the integrated USB PHY is coupled to the host device through a bus voltage pin adapted to generate a core level signal indicating a valid bus voltage from the host device.

5. The regulation apparatus of claim 1 , further comprising:

a comparator configured to generate a core level signal indicating a valid bus voltage from the host device, wherein the comparator is coupled to the control voltage pin.

6. The regulation apparatus of claim 1 , wherein the pass device is a PNP bipolar junction transistor having a base coupled to the control voltage pin and an emitter coupled to the bus voltage.

7. The regulation apparatus of claim 1 , wherein the pass device is a positive-channel field effect transistor having a gate coupled to the control voltage pin and a source coupled to the bus voltage.

8. The regulation apparatus of claim 1 , wherein the integrated USB PHY further comprises:

one or more signal pins configured to connect to a USB connecting cable.

9. The regulation apparatus of claim 5 , wherein the comparator further comprises:

a positive input having a voltage divider coupled to the control voltage pin; and

a negative input having a second voltage divider coupled to a supply voltage pin.

10. A method of generating power for a Universal Serial Bus (USB) system, the method comprising:

receiving, by a pass device, a bus voltage from a host;

supplying, by a regulation circuit coupled to the pass device through an integrated USB physical layer (PHY), substantially 3.3 volts (V) from the bus voltage, the regulation circuit comprising 1.8V input/output (I/O) devices.

11. The method of claim 10 , further comprising:

generating, by a comparator, a core level signal indicating a valid bus voltage from a host device.

12. A method of regu 1 ating a voltage from a pass device, comprising:

providing, to an integrated USB PHY, a control voltage from a bus voltage by a pass device;

dropping the control voltage from the integrated USB PHY with a diode; and

regulating, with a regulation circuit, the dropped control voltage by:

stabilizing, with a cascade device, a node voltage to less than substantially 2 volts; and

dividing, based on the node voltage, a supply voltage to the integrated USB PHY, thereby supplying, a regulated voltage of substantially 3.3 volts to the integrated USB PHY.

13. The method of claim 12 , further comprising:

generating, by a comparator, a core level signal indicating a valid bus voltage from a host device.

14. The method of claim 12 , wherein the generating the core level Signal further comprises:

dividing the control voltage;

providing the divided control voltage to a positive input of the comparator; and

providing the divided supply voltage to a negative input of the comparator.

15. The method of claim 12 , further comprising:

dropping the supply voltage by a second diode, thereby minimizing effects on the pass device from temperature variations.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2011
From: MUELLER, BRIAN K.; BITTING, RICKY F.
To: LSI CORPORATION
Reel/Frame 026798/0100 →
Continuity (1)
Related Publication 20130049838A1 · Feb 28, 2013