Lateral transistor on polymer
Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
1. A device, comprising:
a thin-film semiconductor substrate;
a transistor formed on a first surface of the thin-film semiconductor substrate; and
an insulating polymer layer formed on a second surface of the thin-film semiconductor substrate, the insulating polymer layer having a thickness that is at least twice as thick as a thickness of the thin-film semiconductor substrate.
2. The device of claim 1 , wherein the transistor is a laterally arranged insulated gate bipolar transistor (IGBT).
3. The device of claim 1 , wherein the insulating polymer layer has a larger footprint than a footprint of the thin-film semiconductor substrate.
4. The device of claim 1 , wherein the insulating polymer includes an inorganic filler arranged to increase a thermal conductivity of the insulating polymer.
5. An integrated circuit, comprising:
a laterally arranged high-voltage semiconductor device formed on a first surface of a silicon substrate; and
an insulating silicone layer formed on a second surface of the silicon substrate, a thickness of the silicon substrate being reduced prior to formation of the insulating silicone layer, the insulating silicone layer having a thickness that is at least twice as thick as the thickness of the silicon substrate.
6. The integrated circuit of claim 5 , further comprising another laterally arranged high-voltage semiconductor device formed on the first surface of the silicon substrate, forming a half-bridge arrangement with the laterally arranged high-voltage semiconductor device.
7. The integrated circuit of claim 5 , wherein the thickness of the silicon substrate is reduced to an approximate thickness of between 1 and 30 microns prior to formation of the insulating silicone layer.
8. The integrated circuit of claim 5 , wherein the thickness of the insulating silicone layer is approximately 10 times the thickness of the silicon substrate.
9. A method, comprising:
forming a transistor on a first surface of a semiconductor substrate;
reducing a thickness of the semiconductor substrate from a first thickness to a second lesser thickness; and
forming a polymer layer on a second surface of the semiconductor substrate, the polymer layer having a thickness that is at least twice as thick as the second thickness.
10. The method of claim 9 , further comprising forming at least one of another transistor and a diode on the first surface of the semiconductor substrate.
11. The method of claim 10 , wherein at least one of the other transistor and the diode are serially coupled to the transistor.
12. The method of claim 9 , further comprising reducing a thickness of the semiconductor substrate by grinding the semiconductor substrate in combination with a wet chemical etching.
13. The method of claim 9 , further comprising:
forming an etch stop on the second surface of the semiconductor substrate, the etch stop arranged to define a desired reduced thickness of the semiconductor substrate;
grinding the semiconductor substrate to reduce the thickness of the semiconductor substrate;
chemically etching the semiconductor substrate to further reduce the thickness of the semiconductor substrate to the etch stop; and
removing the etch stop with at least one of a chemical and a mechanical process.
14. The method of claim 13 , wherein the etch stop comprises at least one of a reverse-biased pn junction and a p+ doping.
15. The method of claim 9 , further comprising forming a passivation layer on the second surface of the semiconductor substrate prior to forming the polymer layer.
16. The method of claim 15 , wherein the passivation layer comprises one of a silicon oxide or a silicon nitride.
17. The method of claim 15 , wherein the passivation layer is formed using a plasma-enhanced chemical vapor deposition (PECVD) process.
18. The method of claim 9 , further comprising removing an excess polymer from the first surface of the semiconductor substrate by exposing the excess polymer to a light source and developing the excess polymer.
19. The method of claim 9 , further comprising annealing the polymer layer.
20. The method of claim 9 , wherein the semiconductor substrate is reduced to an approximate thickness of between 1 and 30 microns.
21. The method of claim 9 , wherein the polymer layer comprises a photo imageable silicone layer.
22. The method of claim 9 , wherein the polymer layer has an approximate thickness of between 50 and 150 microns.
23. The method of claim 9 , wherein a thickness of the polymer layer is based on a desired reverse voltage characteristic for the transistor.
24. An integrated circuit, comprising:
at least two serially connected high-voltage semiconductor devices formed on a first surface of a silicon substrate; and
an insulating silicone layer formed on a second surface of the silicon substrate, a thickness of the silicon substrate being reduced prior to formation of the insulating silicone layer, the insulating silicone layer having a thickness that is at least twice as thick as the thickness of the silicon substrate.
25. The integrated circuit of claim 24 , wherein at least one of the serially connected high-voltage semiconductor devices is an insulated gate bipolar transistor (IGBT) and at least another of the serially connected high-voltage semiconductor devices is a diode.