IP Library › Granted Patent US 8,836,013
Granted Patent B2
US 8,836,013 · App. 13/717,429 · Granted Sep 16, 2014

Nonvolatile memory device and method for fabricating the same

Inventor: In-Hey Lee (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L29/7926H01L29/66666H01L21/28H01L29/423H01L21/768H01L27/11582
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Quick Facts
Patent No.
US 8,836,013
App. No.
13/717,429
Granted
Sep 16, 2014
Kind
B2
Abstract

A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.

Claims (11)

1. A nonvolatile memory device, comprising:

a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region;

a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers;

a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes;

a source line formed in the substrate between a plurality of the structures;

a plurality of source contact plugs placed between the plurality of the structures and connected with the source line; and

a well pickup contact plug placed between the plurality of structures and connected with the well region.

2. The nonvolatile memory device of claim 1 , wherein the well pickup contact plug is placed between the plurality of source contact plugs.

3. The nonvolatile memory device of claim 1 , wherein the source contact plugs and the well pickup contact plug extend in a direction substantially identical with a direction of the channel layer.

4. The nonvolatile memory device of claim 1 , wherein the gate electrodes surround a side of the channel layer and extend in one direction.

5. The nonvolatile memory device of claim 1 , further comprising a spacer layer configured to surround sides of each of the source contact plugs and the well pickup contact plug.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: LEE, IN-HEY
To: SK HYNIX INC.
Reel/Frame 029484/0587 →
Priority Claims (1)
KR 10-2012-0088485 · Aug 13, 2012 · national
Continuity (1)
Related Publication 20140042519A1 · Feb 13, 2014