Semiconductor devices including protruding insulation portions between active fins

1. A semiconductor device comprising:

a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions;

first and second multi-channel active fins extending on the field insulation layer, separated from one another by the protruding portion; and

a conductive layer extending from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

2. The semiconductor device of claim 1 wherein the particular distance is greater than a height of uppermost surfaces of the first and second multi-channel active fins beneath respective gates on the first and second multi-channel active fins.

3. The semiconductor device of claim 2 further comprising:

a first source/drain in the first multi-channel active fin directly adjacent to the protruding portion including an uppermost surface that is below the uppermost surface of the protruding portion.

4. The semiconductor device of claim 1 wherein the particular distance is equal to a height of uppermost surfaces of the first and second multi-channel active fins beneath respective gates on the first and second multi-channel active fins.

5. The semiconductor device of claim 4 further comprising:

a first source/drain in the first multi-channel active fin directly adjacent to the protruding portion including an uppermost surface that is above the uppermost surface of the protruding portion.

6. The semiconductor device of claim 1 further comprising:

side wall spacers on the conductive layer; and

a non-planar gate insulation layer between the uppermost surface of the protruding portion and the conductive layer.

7. The semiconductor device of claim 1 wherein the conductive layer is included in a dummy gate.

8. The semiconductor device of claim 1 wherein the conductive layer is included in an active gate.

9. A semiconductor device comprising:

a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions;

first and second multi-channel active fins extending on the field insulation layer, separated from one another by the protruding portion;

a conductive layer extending from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins;

a non-planar insulation layer between the conductive layer and the protruding portion; and

an active gate crossing over the first multi-channel active fin.

10. The semiconductor device of claim 9 wherein the conductive layer is included in a dummy gate located where the conductive layer crosses over the protruding portion.

11. The semiconductor device of claim 9 wherein the particular distance is greater than a height of uppermost surfaces of the first and second multi-channel active fins beneath the active gate and the conductive layer.

12. The semiconductor device of claim 11 further comprising:

a first source/drain in the first multi-channel active fin directly adjacent to the protruding portion including an uppermost surface that is below the uppermost surface of the protruding portion.

13. The semiconductor device of claim 9 wherein the particular distance is equal to a height of uppermost surfaces of the first and second multi-channel active fins beneath the active gate and the conductive layer.

14. The semiconductor device of claim 13 further comprising:

a first source/drain in the first multi-channel active fin directly adjacent to the protruding portion including an uppermost surface that is above the uppermost surface of the protruding portion.

15. A semiconductor device comprising:

an insulation layer including a major surface and a protruding portion protruding from the major surface;

first and second multi-channel active fins directly adjacent to one another and separated from one another by the protruding portion;

a finFET on the first multi-channel active fin;

a conductive layer extending from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins;

a finFET side wall spacer included in the finFET, the finFET side wall spacer having a first height; and

a conductive layer side wall spacer on the conductive layer, the conductive layer side wall spacer having a second height that is less than the first height.

16. The semiconductor device of claim 15 wherein the conductive layer is included in a dummy gate structure.

17. The semiconductor device of claim 15 wherein the conductive layer is included in an active gate structure.

18. The semiconductor device of claim 15 wherein a base of the finFET side wall spacer is below a base of the conductive layer side wall spacer.

19. The semiconductor device of claim 15 further comprising:

an epitaxial source/drain region in the first multi-channel active fin; and

a portion of the first multi-channel active fin, outside the epitaxial source/drain region, between the epitaxial source/drain region and the protruding portion of the insulation layer beneath the conductive layer.

20. The semiconductor device of claim 19 wherein the epitaxial source/drain region is self-aligned to an uppermost portion of the conductive layer side wall spacer.