Continuously self-calibrated latched comparator

1. A comparator apparatus, comprising:

a preamplifier and at least one latched comparator connected to said preamplifier to compare input voltage signals to predefined reference voltage signals, said at least one latched comparator responsive to an offset that limits the minimum input differential voltage signal with respect to said predefined voltage signals;

a calibration component electrically connected to said at least one latched comparator and said preamplifier, wherein said calibration component assists in measuring and compensating said offset in order to calibrate changes in said offset that arise due to electrical variations thereof; and

wherein said at least one latched comparator comprises a delay latch that stores a decision output by said at least one latched comparator, wherein said delay latch stores said decision after sampling a common reference voltage and an input offset with respect to said input voltage signals during a reset phase of said at least one latched comparator.

2. The apparatus of claim 1 wherein said calibration component further assists in compensating said offset in order to continuously calibrate changes in said offset that arise to changes in said electrical variations thereof.

3. The apparatus of dam 1 wherein said decision is utilized in said calibration component for offset compensation during a next reset phase of said at least one latched comparator.

4. The apparatus of claim 1 further comprising at least two charge pumps to provide optimum calibration voltages with respect to said amplifier and a measured input offset.

5. The apparatus of claim 1 further comprising:

at least one switching node; and

a cascode transistor that shields a calibration component voltage associated with said calibration component from said at least one switching node.

6. A comparator apparatus, comprising:

a preamplifier and at least one latched comparator connected to said preamplifier to compare input voltage signals to predefined reference voltage signals, said at least one latched comparator responsive to an offset that limits the minimum input differential voltage signal with respect to said predefined voltage signals;

a calibration component electrically connected to said at least one latched comparator and said preamplifier, wherein said calibration component assists in measuring and compensating said offset in order to calibrate changes in said offset that arise due to electrical variations thereof, and wherein said calibration component further assists in compensating said offset in order to continuously calibrate changes in said offset that arise to changes in said electrical variations thereof;

said at least one latched comparator comprises a delay latch that stores a decision output by said at least one latched comparator;

said delay latch stores said decision after sampling a common reference voltage and an input offset with respect to said input voltage signals during a reset phase of said at least one latched comparator; and

said decision is utilized in said calibration component for offset compensation during a next reset phase of said at least one latched cormparator.

7. The apparatus of claim 6 wherein said at least one latched comparator comprises a delay latch that stores a decision output by said at least one latched comparator.

8. The apparatus of claim 7 wherein said delay latch stores said decision after sampling a common reference voltage and an input offset with respect to said input voltage signals during a reset phase of said at least one latched comparator.

9. The apparatus of claim 7 wherein said decision is utilized in said calibration component for offset compensation during a next reset phase of said at least one latched comparator.

10. The apparatus of claim 6 further comprising at least two charge pumps to provide optimum calibration voltages with respect to said amplifier and a measured input offset.

11. The apparatus of claim 6 further comprising:

at least one switching node; and

a cascode transistor that shields a calibration component voltage associated with said calibration component from said at least one switching node.

12. The apparatus of claim 6 further comprising at least two charge pumps to provide optimum calibration voltages with respect to said amplifier and a measured input offset.

13. The apparatus of claim 6 further comprising:

at least one switching node; and

a cascade transistor that shields a calibration component voltage associated with said calibration component from said at least one switching node.

14. A method of measuring and compensating an offset utilizing a comparator apparatus, said method comprising:

comparing input voltage signals to predefined reference voltage signals via a preamplifier connected to at least one latched comparator, said at least one latched comparator responsive to an offset that limits the minimum input differential voltage signal with respect to said predefined voltage signals; and

measuring and compensating said offset in order to calibrate changes in said offset that arise due to electrical variations thereof via a calibration component electrically connected to said at least one latched comparator and said preamplifier;

a delay latch stores said decision after sampling a common reference voltage and an input offset with respect to said input voltage signals during a reset phase of said at least one latched comparator; and

said decision is utilized in said calibration component for offset compensation during a next reset phase of said at least one latched comparator.

15. The method of claim 14 wherein said calibration component further assists in compensating said offset in order to continuously calibrate changes in said offset that arise to changes in said electrical variations thereof.

16. The method of claim 14 wherein said at least one latched comparator further comprises said delay latch, wherein said delay latch that stores a decision output by said at least one latched comparator.