Isolation layer having a bilayer structure for a semiconductor device and method for forming the same
An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
1. A method for forming an isolation layer of a semiconductor device, comprising the steps of:
forming a hard mask on a semiconductor substrate to expose an isolation region;
forming a trench by etching the exposed isolation region of the semiconductor substrate;
forming a first liner nitride layer on a surface of the trench and the hard mask;
forming a flowable insulation layer on the first liner nitride layer to fill the trench;
performing a chemical mechanical polishing process to remove a portion of the flowable insulation layer and a portion of the first liner nitride layer until the hard mask is exposed;
removing the hard mask;
removing a partial thickness of the chemical mechanical polished flowable insulation layer to form a recess in the trench;
forming a second liner nitride layer on the partially removed flowable insulation layer, the first liner nitride layer and a surface of the recess;
forming an insulation layer on the second liner nitride layer to completely fill the recess; and
removing a portion of the insulation layer formed on the semiconductor substrate and over the trench,
wherein the steps are carried out sequentially in the order listed above.
2. The method according to claim 1 , wherein, after the step of defining the trench and before the step of forming the first liner nitride layer, the method further comprises the step of:
forming a sidewall oxide on the surface of the trench.
3. The method according to claim 1 , wherein in the step of removing a portion of the flowable insulation layer, 200˜2,000 Å of the flowable insulation layer is removed from an upper end of the trench.
4. The method according to claim 1 , wherein in the step of removing a portion of the flowable insulation layer, 500˜1,000 Å of the flowable insulation layer is removed from the upper end of the trench.
5. The method according to claim 1 , wherein the step of removing a partial thickness of the flowable insulation layer is conducted using a wet cleaning process.
6. The method according to claim 1 , wherein the step of removing a partial thickness of the flowable insulation layer is conducted using a dry etching process.
7. The method according to claim 1 , wherein, after the step of removing a partial thickness of the flowable insulation layer and before the step of forming the second liner nitride layer, the method further comprises the step of:
forming a liner oxide layer on the semiconductor substrate, the flowable insulation layer, and the first liner nitride layer.
8. The method according to claim 1 , wherein the second liner nitride layer is formed to have a thickness in the range of 30˜150 Å.
9. The method according to claim 1 , wherein the step of removing the portion of the insulation layer formed on the semiconductor substrate and over the trench is conducted via a chemical mechanical polishing process.
10. The method according to claim 9 , wherein the chemical mechanical polishing process is conducted using a slurry having a polishing selectivity with respect to a nitride layer.
11. The method according to claim 10 , wherein the chemical mechanical polishing process is conducted using a slurry containing an organic polymer additive being one of carbonyl, nitril and amide, and a CeO 2 polishing agent.
12. The method according to claim 1 , wherein after the step of removing the portion of the insulation layer formed on the semiconductor substrate excluding the trench, the method further comprises the step of:
removing a portion of the second liner nitride layer formed on the semiconductor substrate.
13. A method for forming an isolation layer of a semiconductor device, comprising the steps of:
forming a hard mask on a semiconductor substrate to expose an isolation region;
forming a trench by etching the exposed isolation region of the semiconductor substrate;
forming a sidewall oxide on a surface of the trench;
forming a first liner nitride layer on the sidewall oxide and the hard mask;
forming a flowable insulation layer on the first liner nitride layer to fill the trench;
removing a portion of the flowable insulation layer and a portion of the first liner nitride layer until the hard mask is exposed;
removing the hard mask;
removing a partial thickness of the flowable insulation layer to form a recess in the trench and an upper portion of the sidewall oxide between the first liner nitride layer and the surface of the trench;
forming a liner oxide layer on the partially removed flowable insulation layer, the first liner nitride layer and a surface of the recess:
forming a second liner nitride layer on the liner oxide layer;
forming an insulation layer on the second liner nitride layer to completely fill the recess; and
removing the portion of the insulation layer formed on the semiconductor substrate and over the trench.
14. The method according to claim 13 , wherein removing a portion of the flowable insulation layer and a portion of the first liner nitride layer is performed via a chemical mechanical polishing process.