Staggered oxide semiconductor TFT semiconductor device and manufacturing method thereof
View Patent ↗A method for forming a thin film transistor includes steps of forming a first wiring layer over a first electrode layer and forming a second wiring layer over a second electrode layer, wherein the first electrode layer extends beyond an end portion of the first wiring layer, the second electrode layer extends beyond an end portion of the second wiring layer, and a semiconductor layer is formed so as to be electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer.
1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating film over the gate electrode layer;
a first electrode layer and a second electrode layer whose end portions overlap with the gate electrode layer, over the gate insulating film;
a first wiring layer over the first electrode layer;
a second wiring layer over the second electrode layer; and
an oxide semiconductor layer over the gate electrode layer,
wherein the first electrode layer extends beyond an end portion of the first wiring layer,
wherein the second electrode layer extends beyond an end portion of the second wiring layer,
wherein the oxide semiconductor layer is electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer,
wherein the gate insulating film over the gate electrode layer has a region in contact with the oxide semiconductor layer between a region in contact with the first electrode layer and a region in contact with the second electrode layer,
wherein the oxide semiconductor layer is in contact with a side face and a top face of the first wiring layer and a side face and a top face of the second wiring layer, and
wherein the oxide semiconductor layer is in contact with the side face and the top face of the first electrode layer and the side face and the top face of the second electrode layer.
2. The semiconductor device according to claim 1 ,
wherein a width which is from the end portion of the first electrode layer to the end portion of the first wiring layer or a width which is from the end portion of the second electrode layer to the end portion of the second wiring layer is within the range of from 0.2 μm to 5 μm, inclusive.
3. The semiconductor device according to claim 1 ,
wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm, inclusive; and
wherein a thickness of the first electrode layer or the second electrode layer is within the range of from 5 nm to 200 nm, inclusive.
4. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer is electrically connected to the side face and the top face of the first wiring layer and the side face and the top face of the second wiring layer.
5. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
6. The semiconductor device according to claim 1 ,
wherein a thickness of the first electrode layer and a thickness of the second electrode layer are smaller than a half of a thickness of the oxide semiconductor layer.
7. A semiconductor device comprising:
a first electrode layer and a second electrode layer;
a first wiring layer over the first electrode layer;
a second wiring layer over the second electrode layer;
an oxide semiconductor layer over the first electrode layer and the second electrode layer;
a gate insulating film over the oxide semiconductor layer; and
a gate electrode layer overlapping with end portions of the first electrode layer and the second electrode layer with the gate insulating film therebetween,
wherein the first electrode layer extends beyond an end portion of the first wiring layer,
wherein the second electrode layer extends beyond an end portion of the second wiring layer,
wherein the oxide semiconductor layer is electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer,
wherein the oxide semiconductor layer is in contact with a side face and a top face of the first wiring layer and a side face and a top face of the second wiring layer, and
wherein the oxide semiconductor layer is in contact with the side face and the top face of the first electrode layer and the side face and the top face of the second electrode layer.
8. The semiconductor device according to claim 7 ,
wherein a width which is from the end portion of the first electrode layer to the end portion of the first wiring layer or a width which is from the end portion of the second electrode layer to the end portion of the second wiring layer is within the range of from 0.2 μm to 5 μm, inclusive.
9. The semiconductor device according to claim 7 ,
wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm, inclusive, and
wherein a thickness of the first electrode layer or the second electrode layer is within the range of from 5 nm to 200 nm, inclusive.
10. The semiconductor device according to claim 7 ,
wherein the oxide semiconductor layer is electrically connected to the side face and the top face of the first wiring layer and the side face and the top face of the second wiring layer.
11. The semiconductor device according to claim 7 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
12. The semiconductor device according to claim 7 ,
wherein a thickness of the first electrode layer and a thickness of the second electrode layer are smaller than a half of a thickness of the oxide semiconductor layer.