IP Library Granted Patent US 8,847,303
Granted Patent B2
US 8,847,303 · App. 13/422,294 · Granted Sep 30, 2014

Semiconductor device and method for manufacturing the same

Inventors: Masaru Kito (Mie-ken, JP); Ryota Katsumata (Mie-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/7926H01L27/1157H01L27/11582
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Quick Facts
Patent No.
US 8,847,303
App. No.
13/422,294
Granted
Sep 30, 2014
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.

Claims (27)

1. A semiconductor device comprising:

a substrate;

a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate;

an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction;

a channel body provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of an insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole; and

a semiconductor layer that is formed of a same material as the channel body and is embedded in the hole above the part where the channel body blocks the hole the semiconductor layer continuously and integrally provided on the part where the channel body blocks the hole,

an impurity concentration of the semiconductor layer and an impurity concentration of the part where the channel body blocks the hole being higher than an impurity concentration of another part of the channel body other than the part where the channel body blocks the hole.

2. The device according to claim 1 , wherein a diameter of the hole is narrowest near the end of the insulating layer side in the selector gate.

3. The device according to claim 1 , wherein there is no interface between the channel body and the semiconductor layer, and a natural oxide film is not interposed.

4. The device according to claim 1 , wherein the channel body is directly exposed to the cavity.

5. The device according to claim 1 , wherein the channel body and the semiconductor layer are made of contiguous and integral polycrystalline silicon.

6. A semiconductor device comprising:

a substrate;

a first stacked body having a plurality of electrode layers and a plurality of first insulating layers stacked above the substrate so as to be respectively alternating;

a memory film provided on a sidewall of a first hole formed by penetrating the first stacked body in the stacking direction;

a second stacked body provided on the first stacked body, including a selector gate and a second insulating layer provided on the selector gate;

an insulating film provided on a sidewall of a second hole that communicates with the first hole by penetrating the second stacked body in the stacking direction,

a channel body provided on a sidewall of the memory film in the first hole and on a sidewall of the insulating film in the second hole, that blocks the second hole near an end of a second insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the second hole; and

a semiconductor layer that is formed of a same material as the channel body, is embedded in the second hole above the part where the channel body blocks the second hole, the

semiconductor lager continuously and integrally provided on the part where the channel body blocks the second hole,

an impurity concentration of the semiconductor layer and an impurity concentration of the part where the channel body blocks the second hole being higher than an impurity concentration of another part of the channel body other than the part where the channel body blocks the second hole.

7. The device according to claim 6 , wherein the cavity is provided in the first hole and in the second hole.

8. The device according to claim 6 , wherein the memory film and the insulating film include a stacked film in which a charge accumulation film is sandwiched by a pair of silicon oxide films.

9. The device according to claim 6 , wherein a diameter of the second hole is narrowest near the end of the second insulating layer side in the selector gate.

10. The device according to claim 6 , wherein there is no interface between the channel body and the semiconductor layer, and a natural oxide film is not interposed.

11. The device according to claim 6 , wherein the channel body is directly exposed to the cavity.

12. The device according to claim 6 , wherein the channel body and the semiconductor layer are made of contiguous and integral polycrystalline silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2012
From: KITO, MASARU; KATSUMATA, RYOTA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 027877/0475 →
Priority Claims (1)
JP 2011-250475 · Nov 16, 2011 · national
Continuity (1)
Related Publication 20130119456A1 · May 16, 2013