Semiconductor integrated circuit and fabricating the same

1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

receiving a precursor, the precursor including:

a substrate;

conductive features extending above the substrate; and

a space between the conductive features;

depositing a decomposable polymer layer (DPL) in the space between the conductive features on the precursor;

annealing the DPL to form an ordered periodic pattern of different types of polymer nanostructures between the conductive features;

performing a first selective etch to decompose a first type of the polymer nanostructures to form a trench and a template with the ordered repeating periodic pattern of the trench and a second type of polymer nanostructures between conductive features;

filling in the trench with a dielectric layer to form a dielectric block; and

performing a second selectively etching to decompose the second type of polymer nanostructures to form a dielectric matrix of nano-air gaps and the dielectric block between constructive features.

2. The method of claim 1 , wherein the conductive features include copper lines.

3. The method of claim 1 , wherein the DPL includes a block co-polymer (BCP) layer.

4. The method of claim 3 , wherein the BCP layer includes one or more materials from the group consisting of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polyethyleneoxide-block-polyisoprene (PEO-b-PI), polyethyleneoxide-block-polybutadiene (PEO-b-PBD), polyethyleneoxide-block-polystyrene (PEO-b-PS), polyethyleneoxide-block-polymethylmethacrylate (PEO-b-PMMA), polyethyleneoxide-block-polyethylethylene (PEO-b-PEE), polystyrene-block-polyvinylpyridine (PS-b-PVP), polystyrene-block-polyisoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyferrocenyldimethylsilane (PS-b-PFS), polybutadiene-block-polyvinylpyridine (PBD-b-PVP), and polyisoprene-block-polymethylmethacrylate (PI-b-PMMA).

5. The method of claim 3 , wherein first and second polymer blocks are formed by annealing to the BCP layer with a first temperature.

6. The method of claim 5 , wherein the first and second polymer blocks include a PS block and a PMMA block.

7. The method of claim 6 , wherein the PMMA block is decomposed by oxygen plasma etch.

8. The method of claim 5 , wherein the PS block is decomposed by annealing with a second temperature.

9. The method of claim 8 , wherein the second temperature is substantial higher than the first temperature.

10. The method of claim 3 , further comprising:

depositing a neutralize layer (NL) prior to depositing the BCP layer.

11. The method of claim 1 , wherein the nano-air gap is formed with a width that is less than 100 nm.

12. The method of claim 1 , wherein the trench is filled by a low k (LK) dielectric material.

13. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

receiving a precursor, the precursor including a substrate, conductive features extending above the substrate, and a space between conductive features;

depositing a neutralize layer (NL) on the space between the conductive features;

depositing a block co-polymer (BCP) layer over the NL;

annealing the BCP layer with a first temperature to form an ordered periodic pattern of a first and second polymer blocks on the space between the conductive features;

performing a first selective etch to decompose the second polymer block to form a trench and a template with an ordered periodic repeating pattern of the trench and the first polymer block;

filling in the trench with a dielectric layer to form a dielectric block; and

performing a second selective etch to decompose the first polymer block to form a dielectric matrix with nano-air gaps and the dielectric blocks.

14. The method of claim 13 , wherein the BCP layer includes one or more materials from the group consisting of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polyethyleneoxide-block-polyisoprene (PEO-b-PI), polyethyleneoxide-block-polybutadiene (PEO-b-PBD), polyethyleneoxide-block-polystyrene (PEO-b-PS), polyethyleneoxide-block-polymethylmethacrylate (PEO-b-PMMA), polyethyleneoxide-block-polyethylethylene (PEO-b-PEE), polystyrene-block-polyvinylpyridine (PS-b-PVP), polystyrene-block-polyisoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyferrocenyldimethylsilane (PS-b-PFS), polybutadiene-block-polyvinylpyridine (PBD-b-PVP), and polyisoprene-block-polymethylmethacrylate (PI-b-PMMA).

15. The method of claim 13 , wherein the first selective etch includes oxygen plasma etch.

16. The method of claim 13 , wherein the second selective etch includes an annealing with a second temperature, which is substantially higher than the first temperature.

17. The method of claim 13 , wherein the second selective etch includes a wet etch containing solutions of sulfuric acid (H2SO4) and peroxide (H2O2).

18. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

receiving a substrate

forming conductive features above the substrate, with a space between the conductive features;

depositing a neutralize layer (NL) in the space between the conductive features;

depositing a decomposable polymer layer (DPL) over the NL;

annealing the DPL;

performing a first selective etch of the annealed DPL to form a trench;

filling in the trench with a dielectric layer; and

performing a second selectively etching to form a dielectric matrix of nano-air gaps.

19. The method of claim 18 , wherein the DPL includes a block co-polymer (BCP).

20. The method of claim 18 , wherein the DPL includes a block co-polymer (BCP).

21. The method of claim 18 , wherein the dielectric layer forms a dielectric block.