Three dimensional semiconductor memory device and method of manufacturing the same

1. A semiconductor device, comprising:

a first source layer;

at least one of a second source layer, the second source layer formed substantially in the first source layer;

a plurality of conductive layers stacked substantially over the first source layer;

channel layers that pass through the plurality of conductive layers and couple to the second source layer; and

at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

2. The semiconductor device of claim 1 , wherein at least one of a lowermost conductive layer, from the conductive layers, is configured as a lower select line, at least one of an uppermost conductive layer, is configured as an upper select line, and remaining conductive layers are configured as word lines.

3. The semiconductor device of claim 1 , further comprising a memory layer substantially surrounding outer surfaces of the channel layers and an outer surface of the second source layer.

4. The semiconductor device of claim 1 , further comprising at least one slit located between the channel layers adjacent to each other, wherein the slit passes through the conductive layers, the second source layer, and extends to the first source layer.

5. The semiconductor device of claim 4 , wherein the third source layer substantially fills a lower portion of the first slit and is directly coupled to the first source layer.

6. The semiconductor device of claim 1 , further comprising second slits located between a plurality of the second source layers adjacent to each other, wherein each of the second slits has a depth extending through the plurality of conductive layers.

7. The semiconductor device of claim 1 , wherein the second source layer substantially surrounds the third source layer and the second source layer includes at least one first opening substantially in the form of an island in a bottom surface of the second source layer and at least one second opening substantially in the form of a line in a top surface thereof.

8. The semiconductor device of claim 7 , wherein the third source layer comprises:

a plate layer formed substantially in the at least one second source layer; and

a protruding layer substantially protruding from a bottom surface of the plate layer and coupled to the first source layer through the first opening, wherein the protruding layer is substantially in the form of an island.

9. The semiconductor device of claim 1 , wherein the second source layer substantially surrounds the third source layer and the second source layer includes at least one of a first opening substantially in the form of a line in a bottom surface of the second source layer and at least one of a second opening substantially in the form of a line in a top surface thereof.

10. The semiconductor device of claim 9 , wherein the third source layer comprises:

a plate layer formed substantially in the second source layer; and

at least one protruding layer protruding from a bottom surface of the plate layer and coupled to the first source layer through the first opening, wherein the protruding layer is substantially in the form of a line.

11. The semiconductor device of claim 1 , further comprising:

first contact plugs coupled to the plurality of conductive layers; and

at least one of a second contact plug coupled to the third source layer.

12. has been amended as follows: A semiconductor device, comprising:

a first conductive layer;

a semiconductor layer divided into a horizontal region, in which the semiconductor layer surrounds an outer surface of the first conductive layer, and a vertical region which begins protruding from a top surface of the first conductive layer;

a multi-layer insulating layer surrounding an outer surface of the semiconductor layer; and

a plurality of second conductive layers surrounding the vertical region of the semiconductor layer and stacked with the multi-layer insulating layer interposed therebetween, wherein

the first conductive layer passes through the semiconductor layer and the multi-layer insulating layer,

the first conductive layer passes through the semiconductor layer and the multi-laver insulating layer and is coupled to a third conductive laver, and

the first conductive layer and the horizontal region of the semiconductor layer are configured as source lavers, the vertical region of the semiconductor layer is configured as a channel layer, the plurality of second conductive layers are configured as a word lines or select lines, and the multilayer insulating layer is configured as a memory layer.

13. The semiconductor device of claim 12 , wherein the horizontal region of the semiconductor layer is doped with impurities.

14. has been amended as follows: The semiconductor device of claim 12 , wherein the third conductive layer is substantially surrounding the first conductive layer with the multi-layer insulating layer interposed therebetween.

15. The semiconductor device of claim 14 , wherein the first conductive layer is coupled to the third conductive layer.

16. has been amended as follows: The semiconductor device of claim 14 , wherein the third conductive layer is configured as a source layer.