Low latency multi-detector noise cancellation
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.
1. A data processing circuit, comprising:
a first data detector circuit operable to perform a data detection process on a first signal derived from a data input to yield a detected output;
a second data detector circuit operable to perform a data detection process on a second signal derived from the data input to yield a second detected output;
an error cancellation circuit operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal; and
a summation circuit operable to subtract the feedback signal from the data input.
2. The data processing circuit of claim 1 , wherein a first data detector circuit latency is greater than a second data detector circuit latency.
3. The data processing circuit of claim 1 , wherein the error cancellation circuit comprises:
a delay circuit operable to delay the second error signal to yield a delayed second error signal; and
a summation circuit operable to add the first error signal and add the second error signal and subtract the delayed second error signal to yield the feedback signal.
4. The data processing circuit of claim 3 , wherein the delay circuit is operable to delay the second error signal to match a delayed second error signal latency with a first error signal latency.
5. The data processing circuit of claim 1 , wherein the first signal and the second signal are the same signal.
6. The data processing circuit of claim 1 , wherein the circuit further comprises:
an analog to digital converter circuit operable to convert the data input into a corresponding digital output;
a digital filter operable to filter the digital output and provide a filtered output;
a scaler operable to scale the digital output by a DC gain of the digital filter and provide a scaled output; and
wherein the first signal is the filtered output, and wherein the second signal is the scaled output.
7. The data processing circuit of claim 6 , wherein the circuit further comprises:
a loop filter circuit operable to filter the feedback signal to yield a filtered feedback signal; and
a digital to analog converter circuit operable to convert the filtered feedback signal into an analog feedback signal, wherein the summation circuit is operable to subtract the analog feedback signal from the data input.
8. The data processing circuit of claim 1 , wherein the second data detector circuit comprises:
a second summation circuit operable to sum the second signal with an interference value to yield a sum;
a comparator circuit operable to receive the sum and to provide the second detected output based at least in part on a value of the sum;
a delay circuit operable to delay the sum by a bit period to yield a delayed output; and
a multiplier circuit operable to multiply the delayed output by an interference coefficient corresponding to a preceding bit period to yield the interference value.
9. The data processing circuit of claim 8 , wherein the second data detector circuit further comprises:
a second delay circuit operable to delay the delayed output to yield a second delayed output; and
a second multiplier circuit operable to multiply the second delayed output by a second interference coefficient corresponding to a second preceding bit period to yield a second interference value, wherein the second summation circuit is further operable to sum the second signal with the second interference value to yield the sum, and wherein the preceding bit period directly precedes a current bit period, and wherein the second preceding bit period directly precedes the preceding bit period.
10. The data processing circuit of claim 1 , wherein the circuit further comprises:
a first partial response target circuit operable to convolve the detected output with a first partial response target to yield a first partial response output;
a second summation circuit operable to subtract the first partial response output from a digital data input derived from the data input to yield the first error signal;
a second partial response target circuit operable to convolve the second detected output with a second partial response target to yield a second partial response output; and
a third summation circuit operable to subtract the second partial response output from the digital data input to yield the second error signal.
11. The data processing circuit of claim 1 , wherein the circuit further comprises a Nyquist detection circuit operable to detect an alternating bit pattern in the second detected output and to set the second detected output to zero when the alternating bit pattern is detected.
12. The data processing circuit of claim 1 , wherein the data processing circuit is implemented as an integrated circuit.
13. The data processing circuit of claim 1 , wherein the data processing circuit is incorporated in a storage device.
14. The data processing circuit of claim 1 , wherein the data processing circuit is incorporated in a data transmission device.
15. A method to process data, the method comprising:
providing a first data detector circuit;
providing a second data detector circuit;
performing a data detection process using the first data detector circuit on a first signal derived from the data to yield a detected output;
performing a second data detection process using the second data detector circuit on a second signal derived from the data to yield a second detected output;
calculating an error value based on a first error signal derived from the detected output and on a second error signal derived from the second detected output;
generating a feedback signal based at least in part on the error value; and
subtracting the feedback signal from the data.
16. The method of claim 15 , wherein a latency between the data and the first error signal is greater than a second latency between the data and the second error signal.
17. The method of claim 16 , wherein calculating the error value comprises:
applying a delay to the second error signal to yield a delayed second error signal;
subtracting the delayed second error signal from the first error signal to yield a corrected error signal; and
adding the second error signal to the corrected error signal to yield the error value.
18. The method of claim 15 , wherein the first error signal is derived from the detected output by convolving the detected output with a first partial response target to yield a first partial response output, and subtracting the first partial response output from a digital data input derived from the data to yield the first error signal, and wherein the second error signal is derived from the second detected output by convolving the second detected output with a second partial response target to yield a second partial response output, and subtracting the second partial response output from the digital data input to yield the second error signal.
19. The method of claim 15 , further comprising monitoring the second detected output for an alternating bit pattern of a predetermined length, and setting the second detected output to zero when the alternating bit pattern is detected.
20. The method of claim 15 , wherein performing the second data detection process comprises reducing interference evident in a current bit that is related to at least one preceding bit in a bit stream using a decision feedback equalizer.
21. The method of claim 15 , further comprising replacing the feedback signal with digital samples of the data when not in a tracking mode.
22. A storage system, the storage system comprising:
a storage medium maintaining a data set;
a read/write head assembly operable to sense the data set on the storage medium and to provide an analog output corresponding to the data set;
an amplifier circuit operable to amplify the analog output to yield a data input;
an analog to digital converter operable to sample the data input to yield a digital data input;
a first data detector circuit operable to perform a first data detection process on a first signal derived from the digital data input to yield a first detected output;
a second data detector circuit operable to perform a second data detection process on a second signal derived from the digital data input to yield a second detected output;
an error cancellation circuit operable to combine a first error signal derived from the first detected output with a second error signal derived from the second detected output to yield a feedback signal; and
a summation circuit operable to subtract the feedback signal from the data input.
23. The storage system of claim 22 , wherein the first data detector circuit comprises a Viterbi detector, and wherein the second data detector circuit comprises a decision feedback equalizer, and wherein the error cancellation circuit comprises:
a delay circuit operable to equalize a latency in the first error signal and a second latency in the second error signal to yield a delayed second error signal; and
a second summation circuit operable to add the first error signal and add the second error signal and subtract the delayed second error signal to yield the feedback signal.