IP Library Granted Patent US 8,865,559
Granted Patent B2
US 8,865,559 · App. 14/165,121 · Granted Oct 21, 2014

Capacitors and methods with praseodymium oxide insulators

Inventors: Kie Y. Ahn (Chappaqua, NY); Leonard Forbes (Corvallis, OR); Arup Bhattacharyya (Essex Junction, VT)
Assignee: Micron Technology, Inc.
H01L28/40H01G4/1209C23C16/40H01G4/33H01G4/085C23C16/308H01L21/31683
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,865,559
App. No.
14/165,121
Granted
Oct 21, 2014
Kind
B2
Abstract

Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Claims (25)

1. A method of forming a capacitor, comprising:

forming a horizontal first electrode on a semiconductor substrate;

forming a dielectric over a portion of the horizontal first electrode, including:

forming at least one chemically adhered monolayer that includes praseodymium; and

oxidizing the at least one chemically adhered monolayer to form a praseodymium oxide monolayer;

forming a second horizontal metal electrode over the dielectric; and

forming interfacial layers between the dielectric and the electrodes.

2. The method of claim 1 , wherein forming interfacial layers includes forming at least one Pr—O—N interfacial layer.

3. The method of claim 2 , wherein forming Pr—O—N interfacial layers includes forming layers including approximately 40 atomic percent praseodymium, approximately 20 atomic percent oxygen, and approximately 40 atomic percent nitrogen.

4. The method of claim 1 , wherein forming interfacial layers includes forming at least one TiN interfacial layer.

5. The method of claim 1 , wherein forming interfacial layers includes forming at least one Ti—Si—N interfacial layer.

6. The method of claim 1 , wherein forming interfacial layers includes forming at least one Pr—Si—O interfacial layer.

7. A method of forming a capacitor, comprising:

forming a trench in a substrate

forming a first electrode within the trench;

forming a dielectric over a portion of the first electrode, including:

forming at least one chemically adhered monolayer that includes praseodymium; and

oxidizing the at least one chemically adhered monolayer to form a praseodymium oxide monolayer;

forming a second metal electrode over the dielectric; and

forming interfacial layers between the dielectric and the electrodes.

8. The method of claim 7 , wherein forming interfacial layers includes forming at least one Pr—O—N interfacial layer.

9. The method of claim 8 , wherein forming Pr—O—N interfacial layers includes forming layers including approximately 40 atomic percent praseodymium, approximately 20 atomic percent oxygen, and approximately 40 atomic percent nitrogen.

10. The method of claim 7 , wherein forming interfacial layers includes forming at least one TiN interfacial layer.

11. The method of claim 7 , wherein forming interfacial layers includes forming at least one Ti—Si—N interfacial layer.

12. The method of claim 7 , wherein forming interfacial layers includes forming at least one Pr—Si—O interfacial layer.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: AHN, KIE Y.; FORBES, LEONARD; BHATTACHARYYA, ARUP
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032977/0519 →
Continuity (3)
Continuation 12946620 · Nov 15, 2010
Continuation 11796289 · Apr 27, 2007
Related Publication 20140138795A1 · May 22, 2014