Device with automatic de-skew capability

1. A device with an automatic de-skew capability, coupled between a source driving device and a timing controller, is used for receiving a data signal and a clock signal from the timing controller for driving a display panel, comprising:

a data signal delay module, which is used for receiving the data signal and generating a plurality of data delay signals, wherein each of the plurality of data delay signals has different phases;

a plurality of data registers, which has a clock signal receiving terminal, for receiving the clock signal, coupled to the data signal delay module, wherein the plurality of data delay signals are used for sampling the clock signal and wherein the plurality of data registers generates a logic value based on a sampling result;

a decoding module, which is coupled to an output terminal of the plurality of data registers used for generating a set of selecting signals; and

a delay signal selecting module, which is coupled to an output terminal of the data signal delay module and outputs a best sampling signal, based on the set of selecting signals, to the source driving device, wherein the sampling result includes a success sampling result and a failure sampling result,

wherein the decoding module calculates logic values of sampling results of the plurality of sampling signals, by a logic calculation, to generate a selecting signal corresponding to the best sampling signal, and the decoding module generates selecting signals D m and D 1 according to a formula (D m =XOR(R m+1 +R 1 ), D 1 =R 1 ), wherein “m” presents integer between 2 to the bit number of the data signal, “XOR” presents exclusive or operation, and “R” presents the value of a plurality of data registers.

2. The device with an automatic de-skew capability of claim 1 , wherein the best sampling signal is a data delay signal, selected from the plurality of data delay signals, which has a rising edge indicating to a center point of a data holding time of the timing signal.

3. The device with an automatic de-skew capability of claim 1 , wherein the success sampling result is defined as a rising edge of a data delay signal indicating to a point located within a data holding time of the clock signal and the failure sampling result is defined as a rising edge of a data delay signal failing to indicate to a point located within a data holding time of the clock signal, while the plurality of data delay signals samples the clock signal.

4. The device with an automatic de-skew capability of claim 1 , wherein a judgment value of a maximum data delay signal is stored in a first register R m+1 , and a judgment value of a median data delay signal is stored in a second register R m , if the second register is not able to sample successfully, phases of the clock signal need to be reversed.

5. The device with an automatic de-skew capability of claim 1 , wherein the device utilizes a binary search to find a range of the best sampling signals.