Method for manufacturing integrated circuit structure with magnetoresistance component
A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening. A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure.
1. A method for manufacturing an integrated circuit structure with a magnetoresistance component, comprising:
providing a substrate;
forming a circuit structure layer on the substrate, the circuit structure layer comprising a metal pad;
forming a dielectric layer on the circuit structure layer;
forming a metal damascene structure in the dielectric layer;
forming an opening in the dielectric layer so as to form a step-drop;
after forming the metal damascene structure and the opening, forming a magnetoresistance material layer on the dielectric layer; and
applying a photolithography process to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure;
conformally forming a passivation layer on the dielectric layer so as to cover the magnetoresistance component and to fill into the opening; and
removing the passivation layer and the dielectric layer above the metal pad so as to expose the metal pad.
2. The method of claim 1 , wherein the substrate is either a silicon substrate or a silicon substrate covered by a dielectric material layer, a silicon germanium (SiGe) layer, a gallium arsenide (GaAs) layer or a silicon carbide (SiC) layer.
3. The method of claim 1 , wherein the circuit structure layer is a metal interconnection structure layer.
4. The method of claim 1 , wherein forming the dielectric layer comprises forming a silicon oxide layer, a silicon nitride layer, or a combination thereof on the circuit structure layer.
5. The method of claim 1 , wherein forming the metal damascene structure comprises a planarization process.
6. The method of claim 1 , wherein the metal damascene structure is a metal structure embedded in the dielectric layer with an exposed top surface.
7. The method of claim 1 , wherein a pattern of the metal damascene structure is line-shaped or a large area with slots.
8. The method of claim 1 , wherein the metal damascene structure is formed by using a single-damascene process or a dual-damascene process.
9. The method of claim 1 , wherein forming the metal damascene structure comprises:
forming a metal structure;
forming a dielectric material layer on the metal structure; and
polishing the dielectric material layer for planarization and expose a top surface of the metal structure.
10. The method of claim 1 , wherein a material of the metal damascene structure is selected from a group consisting of tungsten, copper and aluminum.
11. The method of claim 1 , wherein the opening is located in a scribe-line region.
12. The method of claim 1 , wherein the opening is located above the metal pad.
13. The method of claim 1 , wherein the substrate defines a magnetoresistance array region, and the opening is located in the magnetoresistance array region.
14. The method of claim 1 , wherein a depth of the opening is less than or equal to a thickness of the dielectric layer.
15. The method of claim 1 , wherein a depth of the opening is greater than or equal to a thickness of the dielectric layer.
16. The method of claim 1 , wherein the magnetoresistance component is selected from a group consisting of an anisotropic magnetoresistance (AMR) component, a giant magnetoresistance (GMR) component, a tunneling magnetoresistance (TMR) component and a colossal magnetoresistance (CMR) component.
17. The method of claim 1 , wherein forming the passivation layer comprises forming a silicon nitride layer, a silicon oxide layer, or a combination thereof on the dielectric layer.