Data output timing control circuit for semiconductor apparatus

1. A data output timing control circuit for a semiconductor apparatus comprising:

a phase adjustment unit configured to shift a phase of a read command by as much as a code value of a delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying an external clock by as much as predetermined delay amounts, respectively, delay the shifted read command as much as a variable delay amount, and output a result of delay as an output enable flag signal.

2. The data output timing control circuit according to claim 1 , wherein the variable delay amount is a value obtained by compensating for a data output path delay amount in n (n is a natural number) periods of the external clock.

3. The data output timing control circuit according to claim 1 , further comprising a delay amount calculation unit, wherein:

the delay amount calculation unit is configured to subtract a code value of a counting code, which is obtained by counting the variable delay amount and a data output path delay amount based on the external clock, from a code value of data output delay information and output a result of subtraction as the delay control code; and

the delay amount calculation unit comprises:

a reset pulse delay unit configured to delay an output reset pulse signal for the variable delay amount and the data output path delay amount and generate a delayed output reset pulse signal;

a counter unit configured to start counting in response to the output reset pulse signal and finish counting in response to the delayed output reset pulse signal, and generate the counting code; and

a calculation unit configured to subtract the code value of the counting code from the code value having the data output delay information and output the result of subtraction as the delay control code.

4. The data output timing control circuit according to claim 1 , wherein the phase adjustment unit comprises:

a clock adjustment unit configured to adjust the external clock by as much as the predetermined delay amounts, respectively, and generate a plurality of delayed clocks;

a shift register configured to shift the read command by as much as the code value of the delay control code in sequential synchronization with a first delayed clock to a second delayed clock, where from among the plurality of delayed clocks the first delayed clock is delayed a largest amount and the second delayed clock is delayed a smallest amount; and

a variable delay unit configured to delay the shifted read command by as much as the variable delay amount and output the result of delay as the output enable flag signal.

5. The data output timing control circuit according to claim 4 , wherein the variable delay amount is a value obtained by compensating for the data output path delay amount in n (n is a natural number) periods of the external clock.

6. The data output timing control circuit according to claim 4 , wherein the clock adjustment unit comprises a plurality of delay lines connected in series to delay the external clock, and each of the plurality of delayed clocks is a signal output from any one of the plurality of delay lines.

7. The data output timing control circuit according to claim 4 , wherein the shift register comprises:

a plurality of D flip-flops connected in series to shift the read command,

wherein the plurality of D flip-flops connected in series operate in sequential synchronization with the first delayed clock to the second delayed clock.

8. The data output timing control circuit according to claim 7 , wherein the shift register further comprises:

a MUX configured to select the shift amount of the shifted read command through the plurality of D flip-flops in response to the code value of the delay control code.

9. A data output timing control circuit for a semiconductor apparatus comprising:

a clock adjustment unit configured to adjust an external clock by as much as predetermined delay amounts, respectively, and generate a plurality of delayed clocks;

a shift register configured to shift a read command by as much as a code value of a delay control code in sequential synchronization with a first delayed clock to a second delayed clock, where from among the plurality of delayed clocks the first delayed clock is delayed a largest amount and the second delayed clock is delayed a smallest amount; and

a variable delay unit configured to delay the shifted read command by as much as a variable delay amount and output the result of delay as an output enable flag signal.

10. The data output timing control circuit according to claim 9 , wherein the variable delay amount is a value obtained by compensating for the data output path delay amount in n (n is a natural number) periods of the external clock.

11. The data output timing control circuit according to claim 9 , wherein the clock adjustment unit comprises a plurality of delay lines connected in series to delay the external clock, and each of the plurality of delayed clocks is a signal output from any one of the plurality of delay lines.

12. The data output timing control circuit according to claim 9 , wherein the shift register comprises:

a plurality of D flip-flops connected in series to shift the read command,

wherein the plurality of D flip-flops connected in series operate in sequential synchronization with the first delayed clock to the second delayed clock.

13. The data output timing control circuit according to claim 12 , wherein the shift register further comprises:

a MUX configured to select the shift amount of the shifted read command through the plurality of D flip-flops in response to the code value of the delay control code.