Prevention of DoS attack by a rogue graphics application
A mechanism is described for mitigating the effects of such a DoS attack by detecting a multiple TDR situation within a short duration, identifying the errant virtual machines, and suspending all rendering ability for that virtual machine or set of virtual machines. While the disclosed embodiments are described in the context of virtual machines, the principles may be extended to the general problem of DoS attacks due to TDRs and bugchecks on any physical machine that includes a GPU. For example, DoS attacks can be generated from web sites directly using GPU rendering.
1. A method for preventing a reset of a host virtual machine due to graphics accelerator timeouts, the method comprising:
mapping graphics commands to virtual machines requesting the graphics commands, the graphics commands being executed by a graphics accelerator;
based on the mapping, identifying virtual machines that have requested graphics commands causing at least one timeout detection and recovery process associated with the graphics accelerator;
determining that a number of timeout detection and recovery processes have exceeded a predetermined number within a predetermined time period; and
constraining the identified virtual machines.
2. The method of claim 1 , wherein when a single virtual machine caused the number of timeout detection and recovery processes, said constraining comprises not restarting the single virtual machine.
3. The method of claim 1 , wherein when different virtual machines caused the number of timeout detection and recovery processes, said constraining comprises delaying restart of the different virtual machines for a predetermined delay.
4. The method of claim 3 , wherein said graphics accelerator is a graphics processing unit (GPU).
5. The method of claim 1 , wherein when different virtual machines caused the number of timeout detection and recovery processes, said constraining comprises terminating video rendering components of the different virtual machines.
6. The method of claim 5 , wherein said terminating comprises lazy deletion.
7. The method of claim 1 , wherein said identifying comprises flushing the graphics accelerator.
8. The method of claim 1 , wherein said predetermined number within a predetermined time period are determined as a function of a number of timeout and detection recovery events that cause a reset of the host virtual machine.
9. A computing system comprising:
a computing device comprising at least one processor;
a graphics accelerator;
a memory communicatively coupled to said processor when said system is operational;
said memory having stored therein computer instructions that upon execution by the at least one processor cause:
mapping graphics commands to processes requesting the graphics commands;
based on the mapping, identifying processes causing graphics accelerator timeouts associated with a denial of service attack;
determining that a count of graphics accelerator timeouts have exceeded a predetermined number within a predetermined time period, the predetermined number and the predetermined time period selected so as to indicate a denial of service attack; and
constraining one or more processes causing graphics accelerator timeouts that have exceeded the predetermined number within the predetermined time period.
10. The system of claim 9 , wherein when a single process caused the count of the graphics accelerator timeouts, said constraining comprises not restarting the single process.
11. The system of claim 9 , wherein when different processes caused the count of the graphics accelerator timeouts, said constraining comprises delaying restart of the different processes for a predetermined delay.
12. The system of claim 9 , wherein when different processes caused the count of the graphics accelerator timeouts, said constraining comprises terminating video rendering components of the different processes.
13. The system of claim 12 , wherein said terminating comprises lazy deletion.
14. The system of claim 9 , wherein said identifying comprises flushing the graphics accelerator.
15. The system of claim 9 , wherein said graphics accelerator is a graphics processing unit (GPU).
16. A computer readable storage device storing thereon computer executable instructions for preventing a reset of a host virtual machine due to GPU TDRs, said instructions for:
mapping graphics commands to graphics processes requesting the graphics commands;
based on the mapping, identifying virtual machines causing a GPU TDR based on said mapping;
determining that a count of GPU TDRs have exceeded a predetermined number within a predetermined time period; and
constraining one or more virtual machines causing GPU TDRs that have exceeded the predetermined number within the predetermined time period.
17. The computer readable storage device of claim 16 , wherein when a single virtual machine caused the count of the GPU TDRs, said constraining comprises not restarting the single virtual machine.
18. The computer readable storage device of claim 16 , wherein when different virtual machines caused the count of the GPU TDRs, said constraining comprises delaying restart of the different virtual machines for a predetermined delay.
19. The computer readable storage device of claim 16 , wherein when different virtual machines caused the count of the GPU TDRs, said constraining comprises terminating video rendering components of the different virtual machines.
20. The computer readable storage device of claim 16 , wherein said predetermined number within a predetermined time period are determined as a function of a number of TDRs that cause a system bugcheck of the host virtual machine.