ESD protection device with reduced clamping voltage
View Patent ↗Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q 1 , Q 2 , Q 4 ) in a main ESD current conducting path between a first and a second terminal (T 1 , T 2 ), and further comprises at least one driving transistor (Q 3 ) connected in parallel to at least one of the ESD current conducting transistors (Q 1 ) and provided for conducting a driving current (Ib 2 ) to one or more of the ESD current conducting transistors (Q 3 ) on occurrence of an ESD event.
1. An electrostatic discharge (ESD) protection circuit connected between a first terminal and a second terminal of an electronic circuit and provided for protecting the electronic circuit against an ESD event, the ESD protection circuit comprising:
an ESD current conducting path extending from the first terminal to the second terminal and comprising a plurality of ESD current conducting transistors, each having a base, a collector and an emitter, wherein the ESD current conducting transistors are connected in series and configured for conducting an ESD current on occurrence of an ESD event, and wherein the plurality of ESD current conducting transistors further comprises a first bipolar junction transistor having its base and collector connected to the first terminal and a second bipolar junction transistor having its collector connected to the emitter of the first bipolar junction transistor; and
at least one driving transistor having a base, a collector and an emitter, wherein the at least one driving transistor is connected in parallel to at least one of the ESD current conducting transistors, wherein the at least one driving transistor comprises a third bipolar junction transistor having its base and collector connected to the first terminal and its emitter connected to the base of the second bipolar junction transistor, and wherein the at least one driving transistor is configured for conducting a driving current on occurrence of the ESD event.
2. The ESD protection circuit according to claim 1 , wherein the second bipolar junction transistor has its emitter connected to the second terminal.
3. The ESD protection circuit according to claim 1 , wherein the plurality of ESD current conducting transistors further comprises a fourth bipolar junction transistor having its collector connected to the emitter of the second bipolar junction transistor and its base connected to the emitter of the third bipolar junction transistor.
4. The ESD protection circuit according to claim 3 , wherein the fourth bipolar junction transistor has its emitter connected to the second terminal.
5. The ESD protection circuit according to claim 1 , wherein the plurality of ESD current conducting transistors further comprises a fourth bipolar junction transistor having its collector connected to the emitter of the second bipolar junction transistor; and the at least one driving transistor further comprises a fifth bipolar junction transistor, the fifth bipolar junction transistor having its base and collector connected to the first terminal and having its emitter connected to the base of the fourth bipolar junction transistor.
6. The ESD protection circuit according to claim 5 , wherein the fourth bipolar junction transistor has its emitter connected to the second terminal.
7. The ESD protection circuit according to claim 1 , wherein the plurality of ESD current conducting transistors further comprises a fourth bipolar junction transistor having its collector connected to the emitter of the second bipolar junction transistor; and the at least one driving transistor further comprises a fifth bipolar junction transistor and a sixth bipolar junction transistor, the fifth bipolar junction transistor having its base and collector connected to the first terminal and having its emitter connected to the base of the sixth bipolar junction transistor, the collector of the sixth bipolar junction transistor being connected to the emitter of the third bipolar junction transistor and the emitter of the sixth bipolar junction transistor being connected to the base of the fourth bipolar junction transistor.
8. The ESD protection circuit according to claim 7 , wherein the fourth bipolar junction transistor has its emitter connected to the second terminal.
9. The ESD protection circuit according to claim 1 , wherein an area of the plurality of ESD current conducting transistors is at least twice an area of the at least one driving transistor.
10. The ESD protection circuit according to claim 1 , wherein the ESD protection circuit comprises an upstream row of transistors having their bases and collectors connected to the first terminal and configured as diodes.
11. The ESD protection circuit according to claim 1 , wherein the ESD protection circuit operates as an ESD diode between an input/output terminal and a source voltage terminal of the electronic circuit.
12. The ESD protection circuit according to claim 1 , wherein the ESD protection circuit operates as an ESD power clamp between source voltage terminals of the electronic circuit.