Nonvolatile memory device, method of manufacturing the nonvolatile memory device, and memory module and system including the nonvolatile memory device

1. A method of manufacturing a nonvolatile memory device, the method comprising:

forming a channel hole penetrating through a stacked structure of a plurality of sacrificial insulating layers and a plurality of first insulating layers, the stacked structure disposed on a substrate;

forming a sacrificial spacer on a side wall of the channel hole;

forming a semiconductor channel layer on a sidewall of the sacrificial spacer;

partially etching the sacrificial spacer to expose a first portion of a sidewall of the semiconductor channel layer;

forming a second insulating layer on the first portion of the sidewall of the semiconductor channel layer;

after forming the second insulating layer, etching the plurality of sacrificial insulating layers in the stacked structure and the sacrificial spacer so that a second portion of the sidewall of the semiconductor channel layer is exposed; and

forming a gate conductive layer on the exposed second portion of the sidewall of the semiconductor channel layer,

wherein said forming the gate conductive layer is preceded by forming a gate insulating layer directly on the exposed second portion of the sidewall of the semiconductor channel layer, and

wherein the gate insulating layer extends between the gate conductive layer and the plurality of first insulating layers.

2. A method of manufacturing a nonvolatile memory device, the method comprising:

forming a channel hole penetrating through a stacked structure of a plurality of sacrificial insulating layers and a plurality of first insulating layers, the stacked structure disposed on a substrate;

forming a sacrificial spacer on a side wall of the channel hole;

forming a semiconductor channel layer on a sidewall of the sacrificial spacer;

etching the plurality of sacrificial insulating layers in the stacked structure and the sacrificial spacer so that a sidewall of the semiconductor channel layer is exposed;

forming a gate insulating layer on the exposed sidewall of the semiconductor channel layer; and

forming a gate conductive layer on the gate insulating layer,

wherein an air gap is formed within the gate insulating layer and between the plurality of first insulating layers and the semiconductor channel layer.

3. A method of manufacturing a nonvolatile memory device, the method comprising:

alternately stacking a plurality of sacrificial insulating layers and a plurality of first insulating layers on a substrate;

forming a channel hole by selectively etching the plurality of sacrificial insulating layers and the plurality of first insulating layers;

forming a sacrificial spacer on a side wall of the channel hole;

forming a semiconductor channel layer contacting the sacrificial spacer;

forming a wordline recess by etching the plurality of sacrificial insulating layers and the plurality of first insulating layers;

etching the plurality of sacrificial insulating layers and the sacrificial spacer so that a sidewall of the semiconductor channel layer is exposed;

forming a gate insulating layer on the sidewall of the semiconductor channel layer;

forming a gate conductive layer on the gate insulating layer; and

forming a separating insulating layer filling the wordline recess,

wherein the semiconductor channel layer is disposed in a zigzag pattern, and wherein a supporting insulating layer is in an inverse zigzag pattern, in a space between the semiconductor channel layer and the separating insulating layer.

4. The method of claim 3 , further comprising:

partially etching the sacrificial spacer to expose a first portion of the sidewall of the semiconductor channel layer; and

forming a second insulating layer on the first portion of the sidewall of the semiconductor channel layer,

wherein etching the plurality of sacrificial insulating layers and the sacrificial spacer comprises, after forming the second insulating layer, etching the plurality of sacrificial insulating layers and the sacrificial spacer so that a second portion of the sidewall of the semiconductor channel layer is exposed, and

wherein forming the gate conductive layer comprises forming the gate conductive layer on the exposed second portion of the sidewall of the semiconductor channel layer.

5. The method of claim 4 , wherein partially etching the sacrificial spacer further comprises partially etching the sacrificial spacer to expose a portion of a sidewall of an uppermost one of the plurality of first insulating layers relative to a surface of the substrate.

6. The method of claim 5 , wherein forming the second insulating layer further comprises forming the second insulating layer on the portion of the sidewall of the uppermost one of the plurality of first insulating layers.

7. The method of claim 1 , wherein partially etching the sacrificial spacer further comprises partially etching the sacrificial spacer to expose a portion of a sidewall of an uppermost one of the plurality of first insulating layers relative to a surface of the substrate.

8. The method of claim 7 , wherein forming the second insulating layer further comprises forming the second insulating layer on the portion of the sidewall of the uppermost one of the plurality of first insulating layers.

9. The method of claim 2 , further comprising:

partially etching the sacrificial spacer to expose a portion of a sidewall of an uppermost one of the plurality of first insulating layers relative to a surface of the substrate; and

forming a second insulating layer on the sidewall of the semiconductor channel layer.

10. The method of claim 9 , wherein forming the second insulating layer further comprises forming the second insulating layer on the portion of the sidewall of the uppermost one of the plurality of first insulating layers.