Semiconductor device and manufacturing method involving multilayer contact etch stop

1. A method of manufacturing a semiconductor device, said method comprising:

forming a contact etch stop layer on an active area of a semiconductor substrate, wherein a gate stack having a metal gate and a metal oxide on the metal gate is formed on said semiconductor substrate, said contact etch stop layer including a first silicon nitride layer overlying a silicon oxide layer, a second silicon nitride layer overlying the active area, the silicon oxide layer being sandwiched between the first and second silicon nitride layers;

forming a contact hole extending through an interlayer dielectric layer overlying said first silicon nitride layer by etching using said first silicon nitride layer as a protective layer for said active area;

removing a portion of said first silicon nitride layer being exposed at the bottom of said contact hole using said silicon oxide layer as a protective layer for said active area; and

removing the metal oxide on said metal gate using said second silicon nitride layer as a protective layer for said active area, wherein part of said second silicon nitride layer that overlaps said active area has a reduced remaining thickness as a result of said removing the metal oxide.

2. The method of claim 1 , wherein said first silicon nitride layer has a thickness in a range of 200-400 Å, said second silicon nitride layer has a thickness in a range of 50-100 Å, and said silicon oxide layer has a thickness of 50-100 Å.

3. The method of claim 1 , wherein removing a metal oxide on said metal gate comprising sputtering to form a hole through a metal oxide layer.

4. The method of claim 3 , wherein the sputtering comprises a physical vapor deposition process including a radio frequency power in a range of 100-500 W, a bias voltage in a range of 100-300V, an argon flow rate in a range of 2-3 sccm, and a process time in a range of 10-100 seconds.

5. The method of claim 1 , after removing the metal oxide on said metal gate, further comprising: removing a portion of said second silicon nitride layer being exposed at the bottom of said contact hole by a SiCoNi pre-clean process to expose a surface of said active area.

6. The method of claim 5 , wherein said SiCoNi pre-clean process comprises a flow rate of fluorin nitride in a range of 10-30 sccm, a flow rate of ammonia in a range of 30-100 sccm, a pressure in a range of 2-10 Torr, a power of 10-100 w, and a process time in a range of 10-100 seconds.

7. The method of claim 5 , wherein said active area comprises a preformed metal silicide region, and the exposed surface of said active area is formed in said metal silicide region.

8. The method of claim 5 , wherein said SiCoNi pre-clean process comprises an oxide to silicon nitride selectivity ratio of less than 5:1.

9. A semiconductor device comprising:

a semiconductor substrate having an active area;

a gate stack including a metal oxide and a metal gate positioned between said metal oxide and said semiconductor substrate;

a first silicon nitride layer; a second silicon nitride layer overlying the active area and directly contacting said metal oxide; a silicon oxide layer sandwiched between the first and second silicon nitride layers; and

a contact hole through said contact etch stop layer, wherein said contact hole is formed over said active area.

10. The semiconductor device of claim 9 , wherein said first silicon nitride layer has a thickness of 200-400 Å, said second silicon nitride layer has a thickness of 50-100 Å, said silicon oxide layer has a thickness of 50-100 Å.

11. The semiconductor device of claim 9 , wherein said active area comprises a preformed metal silicide region, and said contact hole is formed over said metal silicide region.

12. The semiconductor device of claim 9 , wherein said gate stack comprises a gate dielectric layer overlying the active area and said metal gate overlying said gate dielectric layer, and said gate dielectric layer comprises a high-k material.

13. The semiconductor device of claim 9 , wherein said contact hole is filled with a conductive material.

14. A method of manufacturing a semiconductor device, said method comprising:

forming a contact etch stop layer on an active area of a semiconductor substrate, wherein a gate stack having a metal gate and a metal oxide on the metal gate is formed on said semiconductor substrate, said contact etch stop layer including a first silicon nitride layer overlying a silicon oxide layer, a second silicon nitride layer overlying the active area, the silicon oxide layer being sandwiched between the first and second silicon nitride layers;

forming a contact hole extending through an interlayer dielectric layer overlying said first silicon nitride layer by etching using said first silicon nitride layer as a protective layer for said active area;

removing a portion of said first silicon nitride layer being exposed at the bottom of said contact hole using said silicon oxide layer as a protective layer for said active area; and

removing the metal oxide on said metal gate using said second silicon nitride layer as a protective layer for said active area,

wherein said first silicon nitride layer has a thickness in a range of 200-400Å, said second silicon nitride layer has a thickness in a range of 50-100Å, and said silicon oxide layer has a thickness in a range of 50-100Å.