Nonvolatile resistive memory element with an integrated oxygen isolation structure
A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.
1. A nonvolatile memory element, comprising:
a first layer operable as an electrode layer and formed above a substrate;
a second layer operable as a variable resistance layer and disposed between the first layer and a third layer operable as an electrode layer;
a fourth layer that is operable as a first oxygen barrier layer disposed between the first layer and the substrate, the fourth layer being configured to prevent the depletion of oxygen vacancies from the first layer; and
a fifth layer that is operable as a second oxygen barrier layer disposed above the third layer, the fifth layer being operable to prevent the depletion of oxygen vacancies from the third layer,
wherein the fourth layer and the fifth layer comprise a material having an amorphous structure, the material comprising amorphous silicon and refractory metal silicon carbides,
wherein the fourth layer interfaces a bottom surface of the first layer, wherein the fourth layer comprises a sixth layer that is operable as a sacrificial layer and comprises a material that is more reactive with oxygen than a material in the second layer, and
wherein the fifth layer interfaces a top surface of the third layer such that the first layer, second layer, and third layer are formed between the fourth layer and the fifth layer.
2. The nonvolatile memory element of claim 1 , wherein the fourth layer has an electrical resistance that is less than the electrical resistance of the second layer when the second layer is in a low-resistance state.
3. The nonvolatile memory element of claim 2 , wherein the electrical resistance of the fourth layer is equal to or less than about 10% of the electrical resistance of the second layer when the second layer is in a low-resistance state.
4. The nonvolatile memory element of claim 1 , wherein the fourth layer comprises a material selected from the group of alloys consisting of tantalum silicon carbide and tungsten silicon carbide.
5. A nonvolatile memory element, comprising:
a first layer operable as an electrode layer and formed above a substrate;
a second layer operable as a variable resistance layer and disposed between the first layer and a third layer operable as an electrode layer;
a fourth layer that is operable as a first sacrificial layer disposed between the first layer and the substrate,
wherein the fourth layer comprises a material that is more reactive with oxygen than a material in the second layer;
a fifth layer that is operable as a first oxygen barrier layer and that is disposed between the fourth layer and the substrate, the fourth layer being configured to prevent the depletion of oxygen vacancies from the first layer;
a sixth layer that is operable as a second sacrificial layer disposed above the third layer, wherein the sixth layer comprises a material that is more reactive with oxygen than a material in the second layer; and
a seventh layer that is operable as a second oxygen barrier layer and that is disposed above the sixth layer, the seventh layer being configured to prevent the depletion of oxygen vacancies from the third layer,
wherein the fifth layer and the seventh layer comprise a material having an amorphous structure, the material comprising amorphous silicon and refractory metal silicon carbides,
wherein the fourth layer interfaces a bottom surface of the first layer,
wherein the fifth layer interfaces a bottom surface of the fourth layer,
wherein the sixth layer interfaces a top surface of the third layer, and
wherein the seventh layer interfaces a top surface of the sixth layer such that the first layer, second layer, and third layer are formed between the fourth layer and the sixth layer.
6. The nonvolatile memory element of claim 5 , wherein the fourth layer comprises amorphous silicon.
7. The nonvolatile memory element of claim 5 , wherein the fourth layer has a thickness no greater than about 7 Å.
8. The nonvolatile memory element of claim 1 , wherein the fifth layer comprises a material having an amorphous structure and an electrical resistance that is less than the electrical resistance of the second layer when the second layer is in a low-resistance state.
9. The nonvolatile memory element of claim 8 , wherein the electrical resistance of the fifth layer is equal to or less than about 10% of the electrical resistance of the second layer when the second layer is in a low-resistance state.
10. The nonvolatile memory element of claim 1 further comprising a word line electrode disposed between the fourth layer and the substrate.
11. The nonvolatile memory element of claim 1 further comprising a bit line electrode disposed above the fifth layer.
12. The nonvolatile memory element of claim 5 further comprising a word line electrode disposed between the fifth layer and the substrate.
13. The nonvolatile memory element of claim 5 further comprising a bit line electrode disposed above the seventh layer.