IP Library › Granted Patent US 8,878,267
Granted Patent B2
US 8,878,267 · App. 13/807,207 · Granted Nov 4, 2014

Solid-state imaging device

Inventor: Fumihiro Inui (Yokohama, JP)
Assignee: Canon Kabushiki Kaisha
H01L27/14643H01L27/14636H01L27/14609H01L27/14632H01L27/14634H01L27/1464
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Quick Facts
Patent No.
US 8,878,267
App. No.
13/807,207
Granted
Nov 4, 2014
Kind
B2
Abstract

A purpose of the present invention is to provide a preferable separation structure of wells when a photoelectric conversion unit and a part of a peripheral circuit unit or a pixel circuit are separately formed on separate substrates and electrically connected to each other. To this end, a solid-state imaging device includes a plurality of pixels including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit; a first substrate on which a plurality of the photoelectric conversion units are disposed; and a second substrate on which a plurality of the amplification transistors are disposed. A well of a first conductivity type provided with a source region and a drain region of the amplification transistor is separated from a well, which is disposed adjacent to the well in at least one direction, of the first conductivity type provided with the source region and the drain region of the amplification transistor.

Claims (25)

1. A solid-state imaging device comprising:

a plurality of pixels, each including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit;

a first substrate on which the plurality of the photoelectric conversion units are disposed; and

a second substrate on which the plurality of the amplification transistors are disposed,

wherein a well of a first conductivity type provided with a source region and a drain region of the amplification transistor is isolated from another well of a first conductivity type which is disposed adjacent to the well in at least one direction, the another well is provided with a source region and a drain region of another amplification transistor,

wherein, between the adjacent wells of the first conductivity type, by disposing a semiconductor region of a second conductivity type, the wells of the first conductivity type are isolated from each other, and

wherein the semiconductor region of the second conductivity type covers a surface which is opposite to a surface on which a gate of the amplification transistor of the two wells of the first conductivity type is provided and extends to a region between the two wells of the first conductivity type.

2. The solid-state imaging device according to claim 1 , wherein a source of the amplification transistor and the well of the first conductivity type are electrically connected to each other.

3. The solid-state imaging device according to claim 1 , further comprising a plurality of reset transistors each configured to reset a voltage of an input node of the amplification transistor,

wherein the plurality of the reset transistors are respectively disposed on the isolated wells of the first conductivity type including the amplification transistors included in the same pixel.

4. The solid-state imaging device according to claim 1 , wherein each pixel includes a selection transistor, and

wherein a plurality of the selection transistors are respectively disposed on the isolated wells of the first conductivity type including the amplification transistor in the same pixel.

5. The solid-state imaging device according to claim 1 , wherein the amplification transistors are disposed in a matrix, and the wells of a first conductive type are isolated from each other between columns of a plurality of amplification transistors.

6. The solid-state imaging device according to claim 1 , wherein the amplification transistors are disposed in a matrix, and the wells of the first conductivity type are isolated from each other between rows of a plurality of the amplification transistors, the solid-state imaging device further comprising a voltage supply unit configured to supply a first voltage and a second voltage that is higher than the first voltage for each of the isolated wells.

7. The solid-state imaging device according to claim 1 , wherein the wells of the first conductive type are isolated for each pixel.

8. The solid-state imaging device according to claim 1 , wherein a source follower circuit is configured with the amplification transistor and a power source.

9. A solid-state imaging device comprising:

a plurality of pixels, each including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit;

a first substrate on which the plurality of the photoelectric conversion units are disposed; and

a second substrate on which the plurality of the amplification transistors are disposed,

wherein a well of a first conductivity type provided with a source region and a drain region of the amplification transistor is isolated from another well of a first conductivity type which is disposed adjacent to the well in at least one direction, the another well is provided with a source region and a drain region of another amplification transistor,

wherein, between the adjacent wells of the first conductivity type, by disposing a semiconductor region of a second conductivity type, the wells of the first conductivity type are isolated from each other,

wherein a source of the amplification transistor and the well of the first conductivity type are electrically connected to each other,

wherein the amplification transistors are disposed in a matrix, and the wells of a first conductive type are isolated from each other between columns of a plurality of amplification transistors, and

wherein the semiconductor region of the second conductivity type covers a surface which is opposite to a surface on which a gate of the amplification transistor of the two wells of the first conductivity type is provided and extends to a region between the two wells of the first conductivity type.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2013
From: INUI, FUMIHIRO
To: CANON KABUSHIKI KAISHA
Reel/Frame 029727/0358 →
Priority Claims (1)
JP 2010-151973 · Jul 2, 2010 · national
Continuity (1)
Related Publication 20130105871A1 · May 2, 2013