Methods of manufacturing a semiconductor device

1. A method of manufacturing a semiconductor device comprising:

forming an alignment mark on a substrate including a first region and a second region, the alignment mark being formed in the second region;

forming an etch target layer including a crystalline material on the alignment mark and the substrate;

partially amorphizing the etch target layer positioned in the first region; and

partially etching the amorphized etch target layer.

2. The method of claim 1 , wherein amorphizing the etch target layer positioned in the first region includes an ion implantation process.

3. The method of claim 2 , wherein the ion implantation process uses silicon (Si), boron (B), phosphor (P), arsenic (As), germanium (Ge) or indium (In) ions.

4. The method of claim 2 , wherein the ion implantation process is conducted by injection energy of about 50 KeV to about 3,000 KeV, with a dose of about 1E15 ions/cm 2 to about 1E16 ions/cm 2 .

5. The method of claim 2 , wherein the ion implantation process is conducted two or more times by changing the injection energy and a kind of the ions.

6. The method of claim 1 , after amorphizing the etch target layer positioned in the first region, further comprising:

forming a photoresist layer on the etch target layer;

aligning the substrate with a photo mask by using the alignment mark; and

partially removing the photoresist layer to form a photoresist pattern through a photolithography process using the photo mask.

7. The method of claim 6 , before forming the photoresist layer, further comprising forming a mask layer on the etch target layer,

and after forming the photoresist layer, further comprising partially removing the mask layer to form a mask through an etching process using the photoresist pattern,

wherein the mask is used as an etching mask while etching the amorphized etch target layer.

8. The method of claim 6 , wherein the alignment mark is a first alignment mark and wherein the photo mask includes a second alignment mark, and the second alignment mark has a position and a shape corresponding to the first alignment mark.

9. The method of claim 1 , wherein forming the etch target layer includes depositing a polysilicon layer or an impurity doped polysilicon layer on the substrate.

10. The method of claim 1 , wherein forming the etch target layer comprises:

forming an amorphous silicon layer or an impurity doped amorphous silicon layer on the substrate; and

crystallizing the amorphous silicon layer or the impurity doped amorphous silicon layer.

11. The method of claim 1 , wherein the alignment mark is formed on an upper portion of the substrate.

12. The method of claim 1 , wherein the alignment mark is formed on the substrate.

13. A method of manufacturing a semiconductor device comprising:

forming a material layer on a substrate having an alignment mark, the material layer comprising an amorphous portion that is laterally offset from the alignment mark and a crystalline portion that is over the alignment mark; and

photolithographically etching the amorphous portion, using the alignment mark that is under the crystalline portion.

14. The method of claim 13 , wherein the photolithographically etching the amorphous portion comprises:

forming a photoresist layer on the material layer;

aligning the substrate with a photo mask using the alignment mark;

patterning the photoresist layer using the photo mask that is aligned with the substrate; and

etching the amorphous portion using the photoresist layer that is patterned.

15. The method of claim 13 , wherein the forming a material layer on the substrate comprises:

forming a crystalline layer on the substrate; and

selectively amorphizing the crystalline layer to form the amorphous portion of the material layer that is laterally offset from the alignment mark.

16. The method of claim 13 , wherein the forming a material layer on the substrate comprises:

forming an amorphous layer on the substrate; and

selectively crystallizing the amorphous layer to form the crystalline portion of the material layer that is over the alignment mark.

17. The method of claim 13 , wherein the material layer comprises elemental silicon.