Shift register and row-scan driving circuit
The present invention discloses a shift register and a row-scan driving circuit including the same, the shift register comprising a first thin film transistor, a second thin film transistor used as an evaluating transistor, a third thin film transistor, a fourth thin film transistor used as a resetting transistor, a first capacitor and a reset voltage controlling unit, wherein the reset voltage controlling unit is used to control the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input from a low voltage signal input when a signal input from a first clock signal input is at low level, a signal input from a second clock signal input is at high level and a signal input from a signal input is at high level.
1. A shift register, comprising:
a first thin film transistor, having a gate connected to a first clock signal input, and a source connected to a signal input;
a second thin film transistor, having a gate connected to a drain of the first thin film transistor, a drain connected to a signal output, and a source connected to a second clock signal input, wherein a clock signal input from the second clock signal input and a clock signal input from the first clock signal input are inverted to each other;
a third thin film transistor, having a gate connected to the drain of the first thin film transistor, a source connected to a high voltage signal input, and a drain connected to a reset voltage controlling unit;
a fourth thin film transistor, having a gate connected to a connection point of the drain of the third thin film transistor and the reset voltage controlling unit, a source connected to the high voltage signal input, and a drain connected to the signal output;
a first capacitor, being connected between the signal output and the gate of the second thin film transistor; and
the reset voltage controlling unit, being connected to a low voltage signal input, the gate of the fourth thin film transistor and the drain of the third thin film transistor, controlling the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input from the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level, and wherein the reset voltage controlling unit comprises:
a fifth thin film transistor, having a gate connected to a charge pump unit, a source connected to the drain of the third thin film transistor and the gate of the fourth thin film transistor respectively, a drain connected to the low voltage signal input; and
the charge pump unit, being connected to the gate of the fifth thin film transistor and the low voltage signal input, dropping the gate voltage of the fifth thin film transistor to such a voltage during a predetermined period, said voltage enables the gate voltage of the fourth thin film transistor to be pulled down by the fifth thin film transistor to a low level corresponding to a voltage input from the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level.
2. The shift register of claim 1 , the charge pump unit comprises:
a sixth thin film transistor, having a drain connected to the low voltage signal input, a gate connected to the drain thereof, and a source connected to the gate of the fifth thin film transistor; and
a seventh thin film transistor, having a gate connected to the gate of the fifth thin film transistor and the source of the sixth thin film transistor respectively, and a drain connected to the first clock signal input, and a source being connected to the drain thereof.
3. The shift transistor of claim 1 , the width to length ratio of channel of the fifth thin film transistor is much smaller than that of the third thin film transistor.
4. The shift transistor of claim 1 , the first capacitor is omitted in the case that the dimension of the second thin film transistor is so large that the parasitic capacitance of the second thin film transistor is sufficient to maintain the gate voltage thereof.
5. The shift register of claim 2 , all the thin film transistors are p-type thin film transistors which are turned on at low level or N-type thin film transistors which are turned on at high level.
6. A row-scan driving circuit, comprises a plurality of cascaded shift registers, wherein a signal input of a first shift register is connected to an initial pulse signal output, a signal input of each of other shift registers is connected to a signal output of the shift register of the preceding stage, the clock signals input from the first clock signal inputs of two adjacent shift registers are inverted to each other, and the clock signals input from the second clock signal inputs of the two adjacent shift registers are inverted to each other; wherein each shift register comprises:
a first thin film transistor, having a gate connected to the first clock signal input, and a source connected to the signal input;
a second thin film transistor, having a gate connected to a drain of the first thin film transistor, a drain connected to the signal output and a source connected to the second clock signal input, wherein a clock signal input from the second clock signal input and a clock signal input from the first clock signal input are inverted to each other;
a third thin film transistor, having a gate connected to the drain of the first thin film transistor, a source connected to a high voltage signal input, and a drain connected to a reset voltage controlling unit;
a fourth thin film transistor, having a gate connected to a connection point of the drain of the third thin film transistor and the reset voltage controlling unit, a source connected to the high voltage signal input, and a drain connected to the signal output;
a first capacitor, being connected between the signal output and the gate of the second thin film transistor; and
the reset voltage controlling unit being connected to a low voltage signal input, the gate of the fourth thin film transistor and the drain of the third thin film transistor respectively, controlling the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input form the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level, and wherein the reset voltage controlling unit comprises:
a fifth thin film transistor, having a gate connected to the charge pump unit, a source connected to the drain of the third thin film transistor and the gate of the fourth thin film transistor respectively, a drain connected to the low voltage signal input; and
a charge pump unit, being connected to the gate of the fifth thin film transistor and the low voltage signal input, dropping the gate voltage of the fifth thin film transistor to such a voltage during a predetermined period, said voltage enables the gate voltage of the fourth thin film transistor to be pulled down by the fifth thin film transistor to a low level corresponding to a voltage input from the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level.
7. The row-scan driving circuit of claim 6 , the charge pump unit comprises:
a sixth thin film transistor, having a drain connected to the low voltage signal input, a gate connected to the drain thereof, and a source connected to the gate of the fifth thin film transistor; and
a seventh thin film transistor, having a gate connected to the gate of the fifth thin film transistor and the source of the sixth thin film transistor respectively, and a drain connected to the first clock signal input, a source connected to the drain thereof.
8. The row-scan driving circuit of claim 6 , the width to length ratio of channel of the fifth thin film transistor is much smaller than that of the third thin film transistor.
9. The row-scan driving circuit of claim 6 , wherein the first capacitor is omitted in the case that the dimension of the second thin film transistor is so large that the parasitic capacitance of the second thin film transistor is sufficient to maintain the gate voltage thereof.
10. The row-scan driving circuit of claim 7 , all the thin film transistors are p-type thin film transistors which are turned on at low level or N-type thin film transistors which are turned on at high level.