Precision resistor for non-planar semiconductor device architecture
Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
1. A method of fabricating a semiconductor structure, the method comprising:
forming first and second semiconductor fins above a substrate;
forming a resistor structure above the first semiconductor fin but not above the second semiconductor fin; and
forming a transistor structure from the second semiconductor fin but not from the first semiconductor fin, the forming comprising:
forming one or more dummy gates above the second semiconductor fin; and, subsequent to forming the resistor structure,
replacing the one or more dummy gates with a permanent gate stack.
2. The method of claim 1 , wherein forming the resistor structure comprises forming a resistive material layer conformal with the first semiconductor fin.
3. The method of claim 2 , wherein forming the resistive material layer comprises forming a polycrystalline silicon layer having a grain size of approximately 20 nanometers.
4. A method of fabricating a semiconductor structure, the method comprising:
forming first and second semiconductor fins above a substrate;
forming an isolation region above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins;
forming a resistor structure above the isolation region but not above the first and second semiconductor fins; and
forming first and second transistor structures from the first and second semiconductor fins, respectively, the forming comprising:
forming one or more dummy gates above the first and second semiconductor fins; and, subsequent to forming the resistor structure,
replacing the one or more dummy gates with a permanent gate stack.
5. The method of claim 4 , wherein forming the resistor structure comprises forming a resistive material layer conformal with the isolation region.
6. The method of claim 5 , wherein forming the resistive material layer comprises forming a polycrystalline silicon layer having a grain size of approximately 20 nanometers.