IP Library › Granted Patent US 8,890,335
Granted Patent B2
US 8,890,335 · App. 14/132,074 · Granted Nov 18, 2014

Semiconductor device

Inventors: Kenji Yokoyama (Kyoto, JP); Takeshi Kawabata (Osaka, JP)
Assignee: Panasonic Corporation
H01L24/20H01L25/0657H01L24/46H01L2224/04105H01L2224/16145H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/73204H01L2224/73265H01L2924/15311H01L2225/0651H01L2225/06513
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Quick Facts
Patent No.
US 8,890,335
App. No.
14/132,074
Granted
Nov 18, 2014
Kind
B2
Abstract

A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

Claims (52)

1. A semiconductor device comprising:

a first semiconductor chip disposed with a circuit formation surface of the first semiconductor chip facing downward;

a second semiconductor chip above which the first semiconductor chip is mounted such that the circuit formation surface of the first semiconductor chip faces a circuit formation surface of the second semiconductor chip;

a base on which the second semiconductor chip is mounted;

a first interconnect having a ring shape and formed on the circuit formation surface of the second semiconductor chip to overlap an outer circumference or part of a circumferential section of a mounting region above which the first semiconductor chip is mounted; and

a second interconnect formed in a region in which the first semiconductor chip faces the second semiconductor chip, the second interconnect extending from the first interconnect to a center section of the first semiconductor chip or the second semiconductor chip, wherein

at the center section of the first semiconductor chip or the second semiconductor chip, the second interconnect is electrically connected to a connection terminal on the circuit formation surface of the first semiconductor chip or the second semiconductor chip, and

the first interconnect and the second interconnect are power supply interconnects or ground interconnects.

2. The semiconductor device of claim 1 , wherein

the second semiconductor chip has a planar dimension larger than the first semiconductor chip.

3. The semiconductor device of claim 1 , wherein

the second interconnect is disposed on the circuit formation surface of the first semiconductor chip.

4. The semiconductor device of claim 1 , wherein

the second interconnect is disposed on the circuit formation surface of the second semiconductor chip.

5. The semiconductor device of claim 1 , wherein

the base is connected to the first interconnect on the second semiconductor chip via a wire.

6. The semiconductor device of claim 1 , wherein

the first interconnect includes a plurality of interconnects.

7. The semiconductor device of claim 1 , wherein

the first interconnect is connected to a plurality of pads on the circuit formation surface of the second semiconductor chip.

8. A semiconductor device comprising:

a first semiconductor chip disposed with a circuit formation surface of the first semiconductor chip facing downward;

a second semiconductor chip which has an extension section formed from a side surface of the second semiconductor chip toward outside, and above which the first semiconductor chip is mounted such that the circuit formation surface of the first semiconductor chip faces a circuit formation surface of the second semiconductor chip;

a base on which the second semiconductor chip is mounted;

a first interconnect having a ring shape and formed on the circuit formation surface of the second semiconductor chip or on an upper surface of the extension section to overlap an outer circumference or part of a circumferential section of a mounting region above which the first semiconductor chip is mounted; and

a second interconnect formed in a region in which the first semiconductor chip faces the second semiconductor chip, the second interconnect extending from the first interconnect to a center section of the first semiconductor chip or the second semiconductor chip, wherein

the second interconnect is electrically connected to a connection terminal on the circuit formation surface of the first semiconductor chip or the second semiconductor chip at the center section of the first semiconductor chip or the second semiconductor chip, and

the first interconnect and the second interconnect are power supply interconnects or ground interconnects.

9. The semiconductor device of claim 8 , further comprising:

a re-distribution interconnect section extending over the circuit formation surface of the second semiconductor chip and the upper surface of the extension section in the region in which the first semiconductor chip faces the second semiconductor chip, the re-distribution interconnect section being electrically connected to the first interconnect.

10. The semiconductor device of claim 8 , wherein

the second interconnect is disposed on the circuit formation surface of the first semiconductor chip.

11. The semiconductor device of claim 8 , wherein

the second interconnect is disposed on the circuit formation surface of the second semiconductor chip.

12. The semiconductor device of claim 8 , wherein

the first interconnect includes a plurality of interconnects.

13. The semiconductor device of claim 8 , wherein

the first interconnect is connected to a plurality of pads on the circuit formation surface of the second semiconductor chip.

14. A semiconductor device comprising:

a first semiconductor chip disposed with a circuit formation surface of the first semiconductor chip facing downward;

a second semiconductor chip which has an extension section formed from a side surface of the second semiconductor chip toward outside, and above which the first semiconductor chip is mounted such that the circuit formation surface of the first semiconductor chip faces a circuit formation surface of the second semiconductor chip;

a base on which the second semiconductor chip is mounted;

a ring interconnect on the circuit formation surface of the second semiconductor chip or on an upper surface of the extension section, the ring interconnect overlapping an outer circumference or part of a circumferential section of a mounting region above which the first semiconductor chip is mounted; and

a re-distribution interconnect section extending over the circuit formation surface of the second semiconductor chip and the upper surface of the extension section in a region in which the first semiconductor chip faces the second semiconductor chip, the re-distribution interconnect being electrically connected to the ring interconnect, wherein

the re-distribution interconnect section is electrically connected to a connection terminal on the circuit formation surface of the first semiconductor chip or the second semiconductor chip at a center section of the first semiconductor chip or the second semiconductor chip, and

the ring interconnect and the re-distribution interconnect section are power supply interconnects or ground interconnects.

15. The semiconductor device of claim 14 , wherein

the ring interconnect includes a plurality of interconnects.

16. The semiconductor device of claim 14 , wherein

the ring interconnect is connected to a plurality of pads on the circuit formation surface of the second semiconductor chip.

17. The semiconductor device of claim 14 , wherein

the base is connected to a pad on the re-distribution interconnect section of the extension section via a wire.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2014
From: YOKOYAMA, KENJI; KAWABATA, TAKESHI
To: PANASONIC CORPORATION
Reel/Frame 032231/0236 →
Priority Claims (1)
JP 2012-057022 · Mar 14, 2012 · national
Continuity (2)
Continuation PCTJP2012005480 · Aug 30, 2012
Related Publication 20140103536A1 · Apr 17, 2014