IP Library › Granted Patent US 8,891,017
Granted Patent B2
US 8,891,017 · App. 14/136,194 · Granted Nov 18, 2014

Video processing apparatus, display apparatus, and video processing method

Inventor: Kazuyoshi Kegasawa (Hara-mura, JP)
Assignee: Seiko Epson Corporation
H04N5/91
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Quick Facts
Patent No.
US 8,891,017
App. No.
14/136,194
Granted
Nov 18, 2014
Kind
B2
Abstract

A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Claims (30)

1. A video processing apparatus comprising:

a video input section that acquires a video signal formed of a plurality of frames;

a frame separator that separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals;

a plurality of parallel processors that perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator; and

a frame combiner that combines the separated video signals on which the plurality of parallel processors have performed the video processing.

2. The video processing apparatus according to claim 1 ,

wherein the frame separator subtracts sync signals corresponding to frames that do not undergo the video processing and outputs the resultant video signals to the plurality of parallel processors.

3. The video processing apparatus according to claim 1 ,

wherein the frame separator subtracts frames that do not undergo the video processing and outputs the resultant video signals to the plurality of parallel processors.

4. The video processing apparatus according to claim 1 ,

wherein the frame separator outputs the video signal to the plurality of parallel processors in a switching operation performed on a frame basis.

5. The video processing apparatus according to claim 1 ,

wherein the video processing includes filtering performed on the video signal and scaling performed on the video signal.

6. The video processing apparatus according to claim 1 ,

wherein each of the plurality of parallel processors performs the video processing on frames that undergo the video processing over a video processing period equal to a frame cycle of the video signal acquired by the video input section multiplied by the number of parallel processors.

7. The video processing apparatus according to claim 1 ,

wherein the frame combiner combines the video signals on which the plurality of parallel processors have performed the video processing sequentially in the order in which the video signals have been inputted.

8. The video processing apparatus according to claim 1 ,

wherein each of the plurality of parallel processors outputs information on a latency in the video processing to the frame combiner, and

the frame combiner combines the video signals based on the information on a latency.

9. A display apparatus comprising:

a video input section that acquires a video signal;

a frame separator that separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals;

a plurality of parallel processors that perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator; and

a frame combiner that combines the separated video signals on which the plurality of parallel processors have performed the video processing.

10. A video processing method comprising:

a first process of causing a video input section to acquire a video signal;

a second process of separating the video signal acquired in the first process on a frame basis and distributing the separated video signals;

a third process of performing video processing in parallel on the separated video signals corresponding to the frames separated and distributed in the second process; and

a fourth process of combining the separated video signals on which the video processing has been performed in the third process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2013
From: KEGASAWA, KAZUYOSHI
To: SEIKO EPSON CORPORATION
Reel/Frame 031828/0852 →
Priority Claims (1)
JP 2013-003254 · Jan 11, 2013 · national
Continuity (1)
Related Publication 20140198255A1 · Jul 17, 2014