Return address optimisation for a dynamic code translator
View Patent ↗A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.
1. A method of optimizing return address translation in a dynamic code translator comprising:
receiving a function call from subject code designed for a first machine having a first hardware environment;
compiling an isoblock including at least target code and compatibility information wherein the target code is designed for a second machine having a second hardware environment which is different from the first hardware environment and the target code includes a subfunction corresponding to the function call;
planting in the target code a trampoline instruction set having a plurality of branch instructions which return a true subject return address conditioned on an isostate of the isoblock stored in an isostate register; and
inserting in the target code instructions which write an address of the trampoline instruction set to a target return address stack of the second machine, instructions which write an address from the subject code directly following the function call to a subject return address register, and instructions which write the isostate of the isoblock to the isostate register when a computed subject return address matches an entry in the subject return address register.
2. The method of claim 1 wherein the instructions which write the address of the trampoline instruction set to the target return address stack include an IP relative target call.
3. The method of claim 2 wherein:
the IP relative target call also writes the address of the trampoline instruction set to a target link register; and
said inserting further inserts instructions which save an existing target return address from the target link register and an existing subject return address from a subject return address register in a translator return address stack, prior to writing the address of the trampoline instruction set to the target link register.
4. The method of claim 1 wherein the isostate register is a non-fix-mapped target register.
5. The method of claim 1 wherein the trampoline instruction set further includes recovery code to find a successor block when the isostate in the isostate register does not match an isostate for any of the branch instructions.
6. The method of claim 1 wherein said planting reserves code area in the trampoline instruction set for a number of compare/branch pairs which is equal to a number of available isostates.
7. The method of claim 1 , further comprising passing the target code including the inserted instructions and trampoline instruction set to the second machine for execution.
8. A computer system comprising:
a first hardware environment including one or more processors which process program instructions and a memory device connected to said one or more processors; and
a dynamic code translator residing in said memory device which optimizes return address translation by receiving a function call from subject code designed for a different computer system having a second hardware environment which is different from the first hardware environment, compiling an isoblock including at least target code and compatibility information wherein the target code is designed for the first hardware environment and includes a subfunction corresponding to the function call, planting in the target code a trampoline instruction set having a plurality of branch instructions which return a true subject return address conditioned on an isostate of the isoblock stored in an isostate register, and inserting in the target code instructions which write an address of the trampoline instruction set to a target return address stack of the second machine, instructions which write an address from the subject code directly following the function call to a subject return address register, and instructions which write the isostate of the isoblock to the isostate register when a computed subject return address matches an entry in the subject return address register.
9. The computer system of claim 8 wherein the instructions which write the address of the trampoline instruction set to the target return address stack include an IP relative target call.
10. The computer system of claim 9 wherein:
the IP relative target call also writes the address of the trampoline instruction set to a target link register; and
said dynamic code translator further inserts instructions in the target code which save an existing target return address from the target link register and an existing subject return address from a subject return address register in a translator return address stack, prior to writing the address of the trampoline instruction set to the target link register.
11. The computer system of claim 8 wherein the isostate register is a non-fix-mapped target register.
12. The computer system of claim 8 wherein the trampoline instruction set further includes recovery code to find a successor block when the isostate in the isostate register does not match an isostate for any of the branch instructions.
13. The computer system of claim 8 wherein said dynamic code translator further reserves code area in the trampoline instruction set for a number of compare/branch pairs which is equal to a number of available isostates.
14. The computer system of claim 8 wherein said dynamic code translator further passes the target code including the inserted instructions and trampoline instruction set to the first hardware environment for execution.
15. A computer program product comprising:
a computer-readable storage medium; and
a dynamic code translator residing in said storage medium which optimizes return address translation by receiving a function call from subject code designed for a first computer system having a first hardware environment, compiling an isoblock including at least target code and compatibility information wherein the target code is designed for a second computer system having a second hardware environment which is different from the first hardware environment and the target code includes a subfunction corresponding to the function call, planting in the target code a trampoline instruction set having a plurality of branch instructions which return a true subject return address conditioned on an isostate of the isoblock stored in an isostate register, and inserting in the target code instructions which write an address of the trampoline instruction set to a target return address stack of the second computer system, instructions which write an address from the subject code directly following the function call to a subject return address register, and instructions which write the isostate of the isoblock to the isostate register when a computed subject return address matches an entry in the subject return address register.
16. The computer program product of claim 15 wherein the instructions which write the address of the trampoline instruction set to the target return address stack include an IP relative target call.
17. The computer program product of claim 16 wherein:
the IP relative target call also writes the address of the trampoline instruction set to a target link register; and
said dynamic code translator further inserts instructions in the target code which save an existing target return address from the target link register and an existing subject return address from a subject return address register in a translator return address stack, prior to writing the address of the trampoline instruction set to the target link register.
18. The computer program product of claim 15 wherein the isostate register is a non-fix-mapped target register.
19. The computer program product of claim 15 wherein the trampoline instruction set further includes recovery code to find a successor block when the isostate in the isostate register does not match an isostate for any of the branch instructions.
20. The computer program product of claim 15 wherein said dynamic code translator further reserves code area in the trampoline instruction set for a number of compare/branch pairs which is equal to a number of available isostates.
21. The computer program product of claim 15 wherein said dynamic code translator further passes the target code including the inserted instructions and trampoline instruction set to the second computer system for execution.