High electron mobility transistor and method of forming the same

1. A semiconductor structure comprising:

a first III-V compound layer;

a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;

a source feature and a drain feature disposed on the second III-V compound layer;

a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode;

a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer; and

a gate dielectric layer disposed over portions of the second III-V compound layer and over an entire top surface of the third III-V compound layer.

2. The semiconductor structure of claim 1 , wherein the carrier channel under the gate electrode comprises a depletion region.

3. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a thickness in a range from about 3 nm to about 20 nm.

4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

5. The semiconductor structure of claim 1 , wherein a width of the third III-V compound layer is less than a width of the gate electrode.

6. The semiconductor structure of claim 1 , wherein the fluorine region depletes a portion of the carrier channel.

7. The semiconductor structure of claim 1 , wherein the gate electrode comprises titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), nickel (Ni), gold (Au) or copper (Cu).

8. The semiconductor structure of claim 1 further comprising a dielectric cap layer, the dielectric cap layer underlying the gate dielectric layer and overlying the second III-V compound layer.

9. The semiconductor structure of claim 1 , wherein each of the source feature and the drain feature are free of Au and comprises Al, Ti or Cu.

10. A semiconductor structure comprising:

a gallium nitride (GaN) layer disposed on a substrate;

an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer, wherein a fluorine region is embedded in the AlGaN layer;

an indium gallium nitride (InGaN) layer disposed on the AlGaN layer;

a P-type GaN layer disposed on the InGaN layer;

a source feature and a drain feature spaced apart and disposed on the AlGaN layer;

a gate electrode disposed over the AlGaN layer between the source feature and the drain feature, wherein the gate electrode is overlying the fluorine region; and

a portion of a gate dielectric layer disposed between the gate electrode and the AlGaN layer, wherein the portion of the gate dielectric layer substantially covers the P-type GaN layer.

11. The semiconductor structure of claim 10 , wherein a carrier channel is located between the GaN layer and the AlGaN layer, the carrier channel comprising a depletion region under the gate electrode.

12. The semiconductor structure of claim 10 , the gate dielectric layer has a thickness in a range from about 3 nm to about 20 nm.

13. The semiconductor structure of claim 10 , wherein the gate dielectric layer comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

14. The semiconductor structure of claim 10 , wherein the portion of the gate dielectric layer overlaps a majority of the fluorine region.

15. The semiconductor structure of claim 10 , wherein each of the source feature and the drain feature are free of Au and comprises Al, Ti or Cu.

16. The semiconductor structure of claim 10 , wherein the gate electrode comprises titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), nickel (Ni), gold (Au) or copper (Cu).

17. The semiconductor structure of claim 10 , wherein a width of the AlGaN layer is less than a width of the gate electrode.

18. A method of forming a semiconductor structure, the method comprising:

epitaxially growing a second III-V compound layer on a first III-V compound layer, the second III-V compound layer being a different composition than the first III-V compound layer, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;

forming a source feature and a drain feature on the second III-V compound layer;

forming a third III-V compound layer on the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer;

depositing a gate dielectric layer on a portion of the second III-V compound layer and an entire top surface of the third III-V compound layer;

treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a fluorine in the second III-V compound layer under the gate electrode; and

forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

19. The method of claim 18 , wherein treating the gate dielectric layer comprising implanting a plurality of dopants having fluorine into the gate dielectric layer and the second III-V compound layer.