Two-stage phase digitizer
View Patent ↗An analog-to-digital converter (ADC) is described. This ADC converts an analog signal into a digital value using a two-pass digitization process. In a first operation, coarse digitization is performed by an averaging converter based on a set of references. Then, in a second operation, fine digitization is performed by either another averaging converter or the same averaging converter based on a subset of the set of references that is progressively closer to an instantaneous value of the analog signal. For example, the coarse digitization may be performed by a low-resolution ADC stage and the fine digitization may be performed by a sigma-delta ADC, such as a single-bit sigma-delta ADC. Moreover, the other averaging converter may use dynamic element matching to shuffle reference elements used to generate the subset. In this way, the ADC may provide high resolution with reduced nonlinearity and quantization noise.
1. An analog-to-digital converter (ADC), comprising:
an averaging converter configured to receive an analog signal and to output a digital value corresponding to the analog signal based on a set of references, wherein the set of references includes a range of values of the analog signal; and
a second averaging converter, electrically coupled to the averaging converter, configured to receive the analog signal and to output a second digital value corresponding to the analog signal based on a second set of references, wherein the second averaging converter is configured to select the second set of references based on the digital value;
wherein the second set of references is a subset of the set of references;
wherein, in aggregate, the second set of references is closer to an instantaneous value of the analog signal than the set of references; and
wherein the averaging converter includes one of: a sigma-delta ADC, a single-slope ADC, a pulse-width modulation ADC, a duty-cycle modulation ADC, and a dual-slope ADC; and
wherein the second averaging converter includes one of a second sigma-delta ADC, a second single-slope ADC, a second pulse-width modulation ADC, a second duty-cycle modulation ADC, and a second dual-slope ADC.
2. The ADC of claim 1 , wherein, using the second set of references, the second digital value output by the second averaging converter has a more linear relationship to the analog signal than the digital value output by the averaging converter.
3. The ADC of claim 1 , wherein the set of references are generated using a set of reference elements and the second set of references are generated using a subset of the set of reference elements; and
wherein the second averaging converter is configured to dynamically select the subset of the set of reference elements used to generate the second set of references.
4. The ADC of claim 1 , wherein the averaging converter includes a sigma-delta ADC and the second averaging converter includes a second sigma-delta ADC; and
wherein at least one of the sigma-delta ADC and the second sigma-delta ADC includes a first-order sigma-delta ADC.
5. The ADC of claim 1 , wherein the averaging converter includes a sigma-delta ADC and the second averaging converter includes a second sigma-delta ADC;
wherein at least one of the sigma-delta ADC and the second sigma-delta ADC includes an n th -order sigma-delta ADC; and
wherein n is greater than one.
6. The ADC of claim 1 , wherein the averaging converter includes a sigma-delta ADC and the second averaging converter includes a second sigma-delta ADC; and
wherein at least one of the sigma-delta ADC and the second sigma-delta ADC includes a single-bit sigma-delta ADC.
7. The ADC of claim 1 , wherein the averaging converter and the second averaging converter are physically implemented by reconfiguring references applied to a single averaging converter;
wherein first references applied to the single averaging converter during a first time interval implement the averaging converter; and
wherein second references applied to the single averaging converter during a subsequent second time interval implement the second averaging converter.
8. The ADC of claim 1 , wherein the second averaging converter includes a phase-domain sigma-delta (PDΣΔ) ADC configured to determine the second digital value based on a phase of the analog signal; and
wherein the second set of references are selected so that the PDΣΔ ADC determines the second digital value in a linear region of operation of the PDΣΔ ADC.
9. The ADC of claim 1 , wherein the second averaging converter is configured to select the second set of references based on the digital value and one of: a look-up table and a nonlinear function.
10. The ADC of claim 1 , wherein the analog signal is provided by a filter having a phase characteristic that is a function of a physical variable.
11. An ADC, comprising:
an averaging converter configured to receive an analog signal and to output digital values corresponding to the analog signal based on a set of references during time intervals, wherein, in a given time interval, the set of references includes a given range of values, and wherein the averaging converter includes one of: a sigma-delta ADC, a single-slope ADC, a pulse-width modulation ADC, a duty-cycle modulation ADC, and a dual-slope ADC; and
control logic, electrically coupled to the averaging converter, configured to dynamically adjust the given range of values during the given time interval based on a digital value corresponding to the analog signal determined in a preceding time interval, wherein the given range of values in the given time interval is less than or equal to another range of values in the preceding time interval.
12. The ADC of claim 11 , wherein the set of references during the given time interval are generated using a subset of a set of reference elements; and
wherein, during the given time interval, the control logic is configured to dynamically select the subset of the set of reference elements used to generate the set of references.
13. The ADC of claim 11 , wherein the averaging converter includes a sigma-delta ADC; and
wherein the sigma-delta ADC includes a first-order sigma-delta ADC.
14. The ADC of claim 11 , wherein the averaging converter includes a sigma-delta ADC;
wherein the sigma-delta ADC includes an n th -order sigma-delta ADC; and
wherein n is greater than one.
15. The ADC of claim 11 , wherein the averaging converter includes a sigma-delta ADC; and
wherein the sigma-delta ADC includes a single-bit sigma-delta ADC.
16. The ADC of claim 11 , wherein the averaging converter includes a PDΣΔ ADC configured to determine the digital values based on a phase of the analog signal; and
wherein the control logic is configured to select the set of references so that the PDΣΔ ADC determines the digital values in a linear region of operation of the PDΣΔ ADC.
17. The ADC of claim 11 , wherein the analog signal is provided by a filter having a phase characteristic that is a function of a physical variable.
18. A method for performing analog-to-digital conversion, comprising:
receiving an analog signal;
using an averaging converter, converting the analog signal into a corresponding digital value based on a set of references, wherein the set of references includes a range of values of the analog signal, wherein the averaging converter includes one of: a sigma-delta ADC, a single-slope ADC, a pulse-width modulation ADC, a duty-cycle modulation ADC, and a dual-slope ADC;
selecting a second set of references based on the digital value, wherein the second set of references span a range of values that is less than the range of values of the analog signal, and wherein the second set of references is a subset of the set of references; and refining the digital value into a second digital value using an averaging converter that converts the analog signal into the corresponding second digital value based on the second set of references.