IP Library Granted Patent US 8,900,405
Granted Patent B2
US 8,900,405 · App. 11/985,579 · Granted Dec 2, 2014

Plasma immersion ion implantation reactor with extended cathode process ring

Inventors: Peter I. Porshnev (San Jose, CA); Majeed A. Foad (Sunnyvale, CA); Kartik Ramaswamy (San Jose, CA); Biagio Gallo (Palo Alto, CA); Hiroji Hanawa (Sunnyvale, CA); Andrew Nguyen (San Jose, CA); Kenneth S. Collins (San Jose, CA); Amir Al-Bayati (San Jose, CA)
Assignee: Applied Materials, Inc.
H01J37/32642H01J37/32412
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Quick Facts
Patent No.
US 8,900,405
App. No.
11/985,579
Granted
Dec 2, 2014
Kind
B2
Abstract

The disclosure concerns a process ring for the wafer support pedestal of a toroidal source plasma immersion ion implantation reactor. The process ring improves edge uniformity by providing a continuous surface extending beyond the wafer edge, in one embodiment. In another embodiment, the process ring includes a floating electrode that functions as an extension of the wafer support electrode by RF coupling at the bias frequency.

Claims (33)

1. A plasma ion immersion plasma reactor, comprising:

a reactor chamber with a ceiling gas distribution plate and a wafer support pedestal with a wafer support surface facing said ceiling gas distribution plate, and an insulated electrode underlying said wafer support surface, said wafer support surface and said ceiling gas distribution plate defining a process zone between them;

a pair of mutually transverse reentrant conduits external of said chamber, each of said conduits being coupled to said chamber at ports on opposing sides of said process zone, and respective RF plasma source power applicators for coupling RF power into the interiors of respective ones of said reentrant conduits;

a dielectric ring surrounding said wafer support surface and having a first dielectric annular ring top surface that is co-planar with or above said wafer support surface, substantially the entirety of said first dielectric annular ring top surface being uncovered, said first dielectric annular ring top surface having an inner diameter that is separated from a circumferential periphery of said wafer support surface by a gap not exceeding about 1% of the diameter of said wafer support surface, said first dielectric annular ring top surface extending beyond a peripheral circumference of said wafer support surface by about 10%-20% of the diameter of said wafer support surface; and

a floating annular electrode inside said ring at a level below said first dielectric annular ring top surface and having an inner circular edge separated by an electrode-to-electrode gap from an outer circular edge of said insulated electrode of said wafer support pedestal.

2. The reactor of claim 1 wherein a radially inner portion of said dielectric ring underlies a peripheral annular portion of a wafer whenever a wafer is placed on said wafer support surface.

3. The reactor of claim 1 further comprising a raised second dielectric annular ring top surface surrounding and contiguous with said first dielectric annular ring top surface, said second dielectric annular ring top surface being displaced above said first dielectric annular ring top surface by a height at least as great as a thickness of a wafer to be held on said wafer support surface.

4. The reactor of claim 3 wherein said height is 1 mm -2 mm.

5. The reactor of claim 3 wherein said height exceeds said thickness of a wafer.

6. The reactor of claim 5 wherein said height is approximately twice said thickness of a wafer.

7. The reactor of claim 1 wherein said wafer support pedestal further comprises a puck layer forming said wafer support surface and formed of an insulating or semi-insulating material, said insulated electrode being enclosed within said puck layer, said reactor further comprising an RF bias power generator coupled to said insulated electrode, said electrode-to-electrode gap being a sufficiently small to enable said floating electrode and said insulated electrode to behave as a single electrode at the frequency of said RF bias power generator.

8. A plasma ion immersion plasma reactor, comprising:

a reactor chamber with a ceiling gas distribution plate and a wafer support pedestal with a wafer support surface and an insulated electrode underlying said wafer support surface, said wafer support surface and said ceiling gas distribution plate defining a process zone between them;

a pair of mutually transverse reentrant conduits external of said chamber, each of said conduits being coupled to said chamber at ports on opposing sides of said process zone, and respective RF plasma source power applicators for coupling RF power into the interiors of respective ones of said reentrant conduits;

a dielectric ring surrounding said wafer support surface and comprising:

(a) a first annular dielectric ring top surface that is co-planar with or above said wafer support surface, substantially the entirety of said first annular dielectric ring top surface being uncovered, said first annular dielectric ring top surface having an inner diameter that is separated from a circumferential periphery of said wafer support surface by a gap not exceeding about 1% of the diameter of said wafer support surface,

(b) a second annular dielectric ring top surface surrounding said first annular dielectric ring top surface, said second annular dielectric ring top surface being displaced above said first annular dielectric ring top surface by a height at least as great as a thickness of a wafer to be held on said wafer support surface,

(c) a floating annular electrode inside said dielectric ring at a level below said first dielectric annular ring top surface and having an inner circular edge separated by an electrode-to-electrode gap from an outer circular edge of said insulated electrode of said wafer support pedestal.

9. The reactor of claim 8 wherein a radially inner portion of said dielectric ring underlies a peripheral annular portion of a wafer whenever a wafer is placed on said wafer support surface.

10. The reactor of claim 9 wherein said height is approximately twice said thickness of a wafer.

11. The reactor of claim 8 wherein said height is 1 mm -2 mm.

12. The reactor of claim 8 wherein said height exceeds said thickness of a wafer.

13. The reactor of claim 8 wherein said wafer support pedestal further comprises a puck layer forming said wafer support surface and formed of an insulating or semi-insulating material, said insulated electrode being enclosed within said puck layer, said reactor further comprising an RF bias power generator coupled to said insulated electrode, said electrode-to-electrode gap being a sufficiently small to enable said floating electrode and said insulated electrode to behave as a single electrode at the frequency of said RF bias power generator.

14. A plasma ion immersion plasma reactor, comprising:

a reactor chamber with a ceiling gas distribution plate and a wafer support pedestal with a wafer support surface facing said ceiling gas distribution plate, and an insulated electrode underlying said wafer support surface, said wafer support surface and said ceiling gas distribution plate defining a process zone between them;

a pair of mutually transverse reentrant conduits external of said chamber, each of said conduits being coupled to said chamber at ports on opposing sides of said process zone, and respective RF plasma source power applicators for coupling RF power into the interiors of respective ones of said reentrant conduits;

a dielectric ring surrounding said wafer support surface and comprising:

(a) a first annular dielectric ring top surface,

(b) a floating annular electrode inside said dielectric ring at a level below said first annular dielectric ring top surface and having an inner circular edge separated by and electrode-to-electrode gap from an outer circular edge of said insulated electrode of said wafer support pedestal.

15. The reactor of claim 14 wherein said wafer support pedestal further comprises a puck layer forming said wafer support surface and formed of an insulating or semi-insulating material, said insulated electrode being enclosed within said puck layer, said reactor further comprising an RF bias power generator coupled to said insulated electrode, said electrode-to-electrode gap being a sufficiently small to enable said floating electrode and said insulated electrode to behave as a single electrode at the frequency of said RF bias power generator.

16. The reactor of claim 15 wherein said first annular dielectric ring top surface is co-planar with or above said wafer support surface.

17. The reactor of claim 14 wherein said dielectric ring comprises a ceramic material.

18. The reactor of claim 14 wherein said insulated electrode and said floating electrode are mutually co-planar.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2008
From: PORSHNEV, PETER I.; FOAD, MAJEED A.; RAMASWAMY, KARTIK; GALLO, BIAGIO; HANAWA, HIROJI; NGUYEN, ANDREW; COLLINS, KENNETH S.; AL-BAYATI, AMIR
To: APPLIED MATERIALS, INC.
Reel/Frame 020578/0366 →
Continuity (1)
Related Publication 20090120367A1 · May 14, 2009