Epitaxial formation mechanisms of source and drain regions
View Patent ↗The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH 4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.
1. A method of forming an integrated circuit, the method comprising:
forming a plurality of gate structures over a substrate;
removing portions of the substrate to form respective recesses adjacent to the plurality of gate structures;
depositing a first epitaxial silicon-containing layer in the recesses, wherein depositing the first epitaxial silicon-containing layer uses a cyclic deposition etching (CDE) process, wherein the CDE process has a CDE unit cycle, wherein the CDE unit cycle has a deposition process and an etch process, wherein the CDE unit cycle uses an etch temperature of the etch process that is different from a deposition temperature of the deposition process in the CDE unit cycle; and
wherein the CDE process includes a deposition, a pump after deposition, an etch, and a pump after etch in each deposition and etch cycle, and wherein the CDE process is performed in the same process chamber; and
depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form respective source and drain regions next to the plurality of gate structures.
2. The method of claim 1 , wherein the etch temperature is higher than the deposition temperature in the CDE unit cycle.
3. The method of claim 2 , wherein the etch temperature used enables no usage of GeH 4 in an etch gas mixture of the etch process.
4. The method of claim 1 , wherein the etch process of the CDE unit cycle uses GeH 4 .
5. The method of claim 1 , wherein the etch temperature is in a range from about 600° C. to about 700° C.
6. The method of claim 1 , wherein the deposition temperature is in a range from about 500 ° C. to about 590° C.
7. The method of claim 1 , wherein a pressure of the etch process is in a range from about 50 Torr to about 500 Torr.
8. The method of claim 1 , wherein a pressure of the deposition process is in a range from about 5 Torr to about 100 Torr.
9. The method of claim 1 , wherein a flow rate of HCl gas used in the etch process is in a range from about 50 sccm to about 30 slm.
10. The method of claim 1 , wherein an etch time for the CDE unit cycle is in a range from about 3 second to about 30 second.
11. The method of claim 1 , wherein etch gases of the etching process of the CDE unit cycle include HCl.
12. The method of claim 1 , wherein the recesses have a depth in a range from about 200 Å to about 400 Å.
13. The method of claim 1 , wherein a thickness of the first epitaxial silicon-containing layer is in a range from about 70 Å to about 300 Å, wherein the first epitaxial silicon-containing layer is doped with phosphorus and carbon, wherein the concentration of the phosphorus is in a range from about 0.3% to about 2%.
14. The method of claim 1 , wherein a resistivity of the first epitaxial silicon-containing layer is in a range from about 0.2 mohm-cm to about 0.6 mohm-cm.
15. A method of forming an integrated circuit, the method comprising:
forming a plurality of gate structures over a substrate;
removing portions of the substrate to form recesses adjacent to the plurality of gate structures;
depositing a first epitaxial silicon-containing layer in the recesses, wherein depositing the first epitaxial silicon-containing layer uses a cyclic deposition etching (CDE) process, wherein the CDE process has a CDE unit cycle, wherein the CDE unit cycle has a deposition process and an etch process, wherein the CDE unit cycle uses an etch temperature of the etch process that is higher than a deposition temperature of the deposition process in the CDE unit cycle; and
wherein the CDE process includes a deposition, a pump after deposition, an etch, and a pump after etch in each deposition and etch cycle, and wherein the CDE process is performed in the same process chamber; and
depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form source and drain regions next to the plurality of gate structures.
16. A method of forming an integrated circuit, the method comprising:
forming a of gate structures over a substrate, the gate structure including a gate dielectric and a gate electrode formed thereon;
forming gate spacers on sidewalls of the gate structure;
using the gate structure and gate spacers as a mask, etching portions of the substrate to form respective recesses aligned with edges of the gate spacers;
depositing a first epitaxial silicon-containing layer in the recesses, wherein depositing the first epitaxial silicon-containing layer uses a cyclic deposition etching (CDE) process, wherein the CDE process has a CDE unit cycle, wherein the CDE unit cycle has a deposition process and an etch process, wherein the CDE unit cycle uses an etch temperature of the etch process that is different from a deposition temperature of the deposition process in the CDE unit cycle; and
wherein the CDE process includes a deposition, a pump after deposition, an etch, and a pump after etch in each deposition and etch cycle, and wherein the CDE process is performed in the same process chamber; and
depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form respective source and drain regions next to the plurality of gate structures.
17. The method of claim 16 , wherein the etch temperature is in a range from about 600° C. to about 700° C. and the deposition temperature is in a range from about 500° C. to about 590° C.
18. The method of claim 16 , wherein a pressure of the etch process is in a range from about 50 Torr to about 500 Torr and a pressure of the deposition process is in a range from about 5 Torr to about 100 Torr.
19. The method of claim 16 , wherein etching portions of the substrate includes undercutting the respective spacers.
20. The method of claim 16 , wherein the etching process uses an etching gas including a gas selected from the group consisting of hydrogen chloride (HCl), chlorine (Cl 2 ), germanium hydride (GeH 4 ), and combinations thereof.