Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method

1. A signal phase adjusting loop, comprising:

a multiphase generator, comprising:

a ring phase shifting loop, having a plurality of output terminals and phase shifting units, for phase-shifting a delayed input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals; and

a phase adjusting circuit, for receiving one of the output clock signals and an input signal, to adjust a phase of the input signal to generate the delayed input clock signal according to a phase of the one of the output clock signals;

wherein the phase adjusting circuit includes:

a controllable delay line, for delaying the input clock signal to adjust the phase of the input signal according to a control signal;

a phase detector, for directly receiving the one of the output clock signals, which has phase substantially the same as the delayed input clock signal, and for detecting phases of the one of the output clock signals and input signal, to generate a phase detecting result; and

a delay control circuit, for generating the control signal according to the phase detecting result.

2. The signal phase adjusting loop of claim 1 , wherein the phase shifting units are phase mixing units.

3. The signal phase adjusting loop of claim 2 , wherein the ring phase shifting loop comprises a plurality of loading match components coupled to the output terminals.

4. The signal phase adjusting loop of claim 2 , wherein the ring phase shifting loop comprises a plurality of latches coupled to the output terminals.

5. The signal phase adjusting loop of claim 1 , wherein the phase shifting units are first latches.

6. The signal phase adjusting loop of claim 5 , wherein the ring phase shifting loop comprises a plurality of loading match components coupled to the output terminals.

7. The signal phase adjusting loop of claim 5 , wherein the ring phase shifting loop comprises at least one second latch coupled between the output terminals.

8. The signal phase adjusting loop of claim 7 , wherein the first latches are different from the second latch.

9. The signal phase adjusting loop of claim 1 , wherein a number of the phase shifting units is twice a number of the output terminals.

10. The signal phase adjusting loop of claim 1 , wherein at least two phase latching units are located between two output terminals.

11. A signal phase adjusting loop, comprising:

a multiphase generator, comprising:

a ring phase shifting loop, having a plurality of output terminals and phase shifting units, for phase-shifting a delayed input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals; and

a phase adjusting circuit, for receiving one of the output clock signals and an input signal, to adjust a phase of the input signal to generate the delayed input clock signal according to a phase of the one of the output clock signals;

wherein the phase shifting units are phase mixing units.

12. The signal phase adjusting loop of claim 11 , wherein the ring phase shifting loop comprises a plurality of loading match components coupled to the output terminals.

13. The signal phase adjusting loop of claim 11 , wherein the ring phase shifting loop comprises a plurality of latches coupled to the output terminals.