Semiconductor device

1. A semiconductor device comprising:

a node to which an input voltage generated in accordance with a DC voltage is supplied;

a P-channel MOS transistor having a drain, a source, and a gate, the drain and the source being coupled between the node and a load circuit, the gate being controlled in accordance with the magnitude of the input voltage;

an N-channel MOS transistor whose drain and source are coupled between the node and the load circuit in parallel with the P-channel MOS transistor; and

a control voltage generation circuit that generates a control voltage not higher than a clamping voltage in accordance with the DC voltage;

wherein the gate of the N-channel MOS transistor is controlled in accordance with the control voltage.

2. The semiconductor device according to claim 1 , wherein the P-channel MOS transistor is defined as a first P-channel MOS transistor, further comprising:

a current mirror circuit having a second P-channel MOS transistor and a third P-channel MOS transistor, the sources of the second and third P-channel MOS transistors being commonly coupled to the node, the gates of the second and third P-channel MOS transistors being mutually coupled;

wherein the drain and the gate of the second P-channel MOS transistor are coupled to a voltage generation circuit that supplies a predetermined voltage to the current mirror circuit; and

wherein the drain of the third P-channel MOS transistor is coupled to a reference power supply through a resistor and coupled to the gate of the first P-channel MOS transistor.

3. The semiconductor device according to claim 2 , wherein the resistor is defined as a first resistor; and wherein the voltage generation circuit includes a diode that is coupled at the anode to the drain and gate of the second P-channel MOS transistor and coupled at the cathode to the reference power supply through a second resistor.

4. The semiconductor device according to claim 2 , wherein the resistor is defined as a first resistor; and wherein the voltage generation circuit includes a zener diode that is coupled at the cathode to the drain and gate of the second P-channel MOS transistor and coupled at the anode to the reference power supply.

5. The semiconductor device according to claim 2 , further comprising:

a power supply shut-off control circuit that, when a detection voltage generated in accordance with the DC voltage is lower than a predetermined voltage, stands by for a predetermined period of time and changes the gate voltage of the first P-channel MOS transistor to a reference power supply voltage.

6. The semiconductor device according to claim 1 , further comprising:

a power supply shut-off control circuit that, when the detection voltage generated in accordance with the DC voltage is higher than a predetermined voltage, stands by for a predetermined period of time and changes the control voltage to the reference power supply voltage.

7. The semiconductor device according to claim 5 , wherein the detection voltage is generated by a voltage divider resistor to which the DC voltage is supplied.

8. The semiconductor device according to claim 5 , wherein the detection voltage is the gate voltage of the first P-channel MOS transistor.

9. The semiconductor device according to claim 1 , wherein the node is defined as a first node; and wherein the control voltage generation circuit includes a zener diode that is coupled at the cathode to a second node to which the DC voltage is supplied through a resistor and to the gate of the N-channel MOS transistor, and is coupled at the anode to a reference power supply.

10. The semiconductor device according to claim 1 , wherein the control voltage generation circuit includes an amplifier circuit that operates on the DC voltage and outputs the result of comparison between a reference voltage and the control voltage as the control voltage.