IP Library › Granted Patent US 8,902,630
Granted Patent B2
US 8,902,630 · App. 13/553,764 · Granted Dec 2, 2014

Semiconductor memory device, semiconductor device and method of manufacturing semiconductor memory device

Inventors: Masaharu Matsudaira (Kanagawa, JP); Masayuki Terai (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L27/10852H01L27/10894H01L45/04H01L45/146H01L45/1683H01L27/2436H01L28/91H01L27/1052
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Quick Facts
Patent No.
US 8,902,630
App. No.
13/553,764
Granted
Dec 2, 2014
Kind
B2
Abstract

In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Claims (15)

1. A semiconductor memory device, comprising:

a variable resistance element of a variable resistance type memory having a cylinder type NUM (Metal-Insulator-Metal) structure with a first depth;

a capacitance element of a DRAM (Dynamic Random Access Memory) having a cylinder type MIM structure with a second depth deeper than the first depth; and

wherein the variable resistance element comprises a first lower electrode, a variable resistance layer provided over the first lower electrode, and a first upper electrode provided over the variable resistance layer,

wherein the capacitance element comprises a second lower electrode, a capacitance insulating film provided over the second lower electrode, and a second upper electrode provided over the capacitance insulating film, and

wherein an end portion of the first upper electrode and an end portion of the second upper electrode are provided in one plane.

2. The semiconductor memory device according to claim 1 , wherein the first lower electrode and the second lower electrode are made using the same material, the variable resistance layer and the capacitance insulating film are made using the same material, and the first upper electrode and the second upper electrode are made using the same material.

3. The semiconductor memory device according to claim 1 , wherein the first lower electrode and a contact coupled to the first lower electrode are made using the same material.

4. The semiconductor memory device according to claim 1 , further comprising:

a first transistor coupled to the variable resistance element; and

a second transistor coupled to the capacitance element,

wherein a withstand voltage of the first transistor is higher than that of the second transistor.

5. The semiconductor device according to claim 1 , wherein the variable resistance type memory is used as a ROM (Read Only Memory).

6. The semiconductor device according to claim 1 , wherein a forming operation of the variable resistance element is performed in order to form a low resistive conductive path in the insulating film.

7. A semiconductor device, comprising: a semiconductor memory device according to claim 1 ; and an information processing circuit which processes information using the semiconductor memory device.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: MATSUDAIRA, MASAHARU; TERAI, MASAYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 028665/0367 →
Priority Claims (1)
JP 2011-209021 · Sep 26, 2011 · national
Continuity (1)
Related Publication 20130077379A1 · Mar 28, 2013