IP Library Granted Patent US 8,904,077
Granted Patent B1
US 8,904,077 · App. 12/111,057 · Granted Dec 2, 2014

Power management for host bus adapters

Inventor: Jerald K. Alston (Coto De Caza, CA)
Assignee: QLOGIC, Corporation
G06F11/1423G06F3/0635
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Quick Facts
Patent No.
US 8,904,077
App. No.
12/111,057
Granted
Dec 2, 2014
Kind
B1
Abstract

Methods and apparatus for reducing power consumption in a host bus adapter (HBA) are provided. The methods include reducing a number of active lanes in an HBA link when link traffic is low, and increasing the number of active lanes when link traffic is high.

Claims (17)

1. A method of allocating bandwidth in a link connecting an adapter with another device in a storage area network (SAN), the method comprising:

a) evaluating an input/output (I/O) request relating to a data transfer between a host system and a storage device in the SAN;

b) determining an amount of data that will be transferred at a given time, including data associated with the I/O request; and

c) enabling or disabling lanes of the link based on the amount of data that will be transferred at the given time, including the data associated with the I/O request;

wherein when link traffic is below a first limit, a first number of lanes are enabled, and more lanes are enabled when the link traffic increases above the first limit.

2. The method of claim 1 , wherein a processor in the adapter performs steps a) through c).

3. The method of claim 1 , wherein firmware in the adapter sets limits for enabling and disabling the lanes.

4. The method of claim 1 , further comprising the step of setting a default bandwidth for the link as the first limit.

5. The method of claim 4 , wherein according to the default bandwidth one of the lanes is enabled and all other lanes are disabled.

6. The method of claim 5 , wherein according to the default bandwidth the enabled lane is enabled at generation 1 (GEN 1) speed.

7. An adapter configured to be connected via a link with another device in a storage area network (SAN), the adapter comprising:

a processor;

wherein the processor is configured to evaluate an input/output (I/O) request relating to a data transfer between a host system and a storage device in the SAN, determine an amount of data that will be transferred at a given time, including data associated with the I/O request, and enable or disable lanes of the link based on the amount of data that will be transferred at the given time, including the data associated with the I/O request.

8. The adapter of claim 7 , wherein when link traffic is low, fewer lanes are enabled and when link traffic is high, more lanes are enabled.

9. The adapter of claim 7 , further comprising firmware in the adapter configured to set limits for enabling and disabling the lanes.

10. The adapter of claim 7 , wherein according to a default bandwidth for the link one of the lanes is enabled and all other lanes are disabled.

11. The adapter of claim 10 , wherein according to the default bandwidth the enabled lane is enabled at generation 1 (GEN 1) speed.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
MERGER Recorded Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
SECURITY AGREEMENT Recorded Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2008
From: ALSTON, JERALD K.
To: QLOGIC, CORPORATION
Reel/Frame 020868/0523 →
Continuity (1)
Provisional Application 60946359 · Jun 26, 2007