Cache with multiple access pipelines
Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
1. A digital system comprising:
a shared resource including a cache subsystem having a shared memory, a first set of access tags and a duplicate second set of access tags;
a first access pipeline coupled to the shared resource, the first access pipeline being configured to receive a first transaction request from a first requester for access to the shared resource, wherein the first access pipeline includes a stall stage that is coupled to the first set of access tags and configured to stall when the first set of access tags indicate a miss in response to the first transaction request;
a second access pipeline coupled to the shared resource, the second access pipeline being configured to receive a second transaction request from a second requester for access to the shared resource, wherein the second access pipeline includes a check stage that is coupled to the second set of access tags, configured to check the second set of access tags and cancel the second transmission request if access is denied; and
arbitration logic configured to control access to the shared resource coupled to the first access pipeline and to the second access pipeline, wherein the arbitration logic is coupled to the first access pipeline after the stall stage and coupled to the second access pipeline after the check stage.
2. The system of claim 1 , wherein:
the arbitration logic includes weighting logic configured to grant access to the shared resource in response to a weighting value stored in a program writable weighting register.