IP Library Granted Patent US 8,907,489
Granted Patent B2
US 8,907,489 · App. 13/603,882 · Granted Dec 9, 2014

Wiring substrate, method of manufacturing the same, and semiconductor device

Inventors: Yuji Kunimoto (Nagano, JP); Naoyuki Koizumi (Nagano, JP)
Assignee: Shinko Electric Industries Co., Ltd.
H01L23/49822H05K2203/025H05K3/4605H01L2924/15311H01L23/49827H01L2224/16225H01L23/49816
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Quick Facts
Patent No.
US 8,907,489
App. No.
13/603,882
Granted
Dec 9, 2014
Kind
B2
Abstract

A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.

Claims (16)

1. A wiring substrate comprising:

a substrate, a material of the substrate consisting of glass or silicon, the substrate having a first surface and a second surface opposite to the first surface, the substrate being formed with a through hole whose diameter is gradually decreased from the first surface to the second surface;

a connection pad formed on the second surface of the substrate;

a first wiring layer formed in the through hole and electrically connected to the connection pad;

a first insulation layer formed on the first surface of the substrate to cover the first wiring layer; and

a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer;

a plurality of insulation layers and a plurality of wiring layers being alternately arranged to form a stack on the first surface side of the substrate; and

a solder resist layer formed on a surface of the stack opposite to the substrate, wherein

the second surface of the substrate is a mounting surface on which a semiconductor chip is to be mounted, and

the first insulation layer formed on the first surface of the substrate is made of a resin material.

2. The wiring substrate of claim 1 , wherein the substrate is made of glass.

3. The wiring substrate of claim 1 , wherein the substrate is made of silicon, the wiring substrate further comprising,

a silicon oxide layer covering the substrate, wherein

the first insulation layer is formed on the first surface of the substrate via the silicon oxide layer,

at the second surface of the substrate, an end surface of the first wiring layer on the second surface side of the silicon substrate and an end surface of the insulation layer on the second surface side of the silicon substrate are flush with each other, and

the connection pad is connected to the end surface of the first wiring layer on the second surface side of the silicon substrate through an opening portion formed in an insulation layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2012
From: KUNIMOTO, YUJI; KOIZUMI, NAOYUKI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 028900/0130 →
Priority Claims (1)
JP 2011-201707 · Sep 15, 2011 · national
Continuity (1)
Related Publication 20130069251A1 · Mar 21, 2013