Manufacturing an underfill in a semiconductor chip package

1. A method for manufacturing an underfill in a semiconductor chip package having a cavity between a first surface and a second surface, the method comprising:

providing a plurality access holes in one of the first or second surface;

providing a plurality vent holes in the one of the first or second surfaces; and

applying a viscous filling material through at least one of the plurality of access holes into the cavity thereby squeezing out air or gas through at least one of the plurality of vent holes;

wherein the access holes and the vent holes are arranged such that each vent hole has a group of nearest-neighbor entry holes having the same distance from the vent hole.

2. The method of claim 1 , further comprising arranging the first and the second surface parallel to each other and essentially horizontally.

3. The method of claim 1 , further comprising arranging the access hole and the vent hole parallel to each other and essentially vertically.

4. The method of claim 1 , further comprising generating a flow of the viscous filling material from the at least one access hole to the at least one vent hole.

5. The method of claim 1 , wherein the applying comprises inserting the viscous filling material downwards in the direction of gravity.

6. The method of claim 1 , further comprising applying the viscous filling material through the access holes such that flow fronts of the viscous filling material reach a vent hole essentially at the same time thereby squeezing a gas or air enclosure through the vent hole or the plurality of vent holes.

7. The method of claim 1 , wherein providing a vent hole and/or an access hole comprises at least of the processes of: drilling, etching, or laser ablation.

8. The method of claim 1 , wherein the first surface and the second surface are spaced by a plurality of solder balls having a predetermined diameter or bumps or rails having a predetermined height.

9. A method for manufacturing an underfill in a semiconductor chip package having a cavity between a first surface and a second surface, the method comprising:

providing at least one access hole in one of the first or second surface;

providing at least one vent hole in the one of the first or second surfaces; and

applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole;

wherein at least one vent hole comprises one of: a filter element for withholding particles in the cavity, and a moderating element for slowing down a flow front of the viscous filling material towards a center of the vent hole.

10. A method for manufacturing an underfill in a semiconductor chip package having a cavity between a first surface and a second surface, the method comprising:

providing at least one access hole in on of the first or second surface;

providing at least one vent hole in the one of the first or second surfaces;

applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole; and

after applying the viscous filler material through the at least one access hole and squeezing out air or gas through a predetermined vent hole, applying the viscous filler material through the predetermined vent hole into the cavity as well thereby employing the predetermined vent hole as an access hole.

11. A method for manufacturing an underfill in a semiconductor chip package having a cavity between a first surface and a second surface, the method comprising:

providing at least one access hole in on of the first or second surface;

providing at least one vent hole in the one of the first or second surfaces;

applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole; and

applying a carrier fluid having immersed filler particles, wherein the filler particles remain in the cavity and arrange according to capillary or convective forces.

12. A semiconductor chip package, comprising:

a cavity between a first surface of a first semiconductor chip and a second surface of a second semiconductor chip or substrate;

at least one access hole in one of the first or second surface, wherein the access hole is adapted to guide a viscous filling material into the cavity; and

at least one vent hole in the one of the first or second surfaces, wherein the vent hole is adapted to let out air or gas from the cavity, and wherein at least one vent hole comprises one of: a filter element for withholding particles in the cavity, and a moderating element for slowing down a flow front of the viscous filling material towards a center of the vent hole.

13. The semiconductor chip package of claim 12 , comprising a plurality of access holes and a plurality of vent holes in the at least one surface.