Clock rate controller and method thereof and electronic device thereof

1. A clock rate control method, comprising:

detecting a usage of a first-input-first-output (FIFO) buffer in an electronic device;

determining whether the usage falls within a first specific interval, wherein the first specific interval has a first upper limit value and a first lower limit value;

when the usage is larger than the first upper limit value, increasing a clock rate of an internal device of the electronic device;

when the usage is less than the first lower limit value, decreasing the clock rate;

when the usage falls within the first specific interval, calculating a deviation value between a current differential value and a previous differential value, and determining whether the deviation value falls within a second specific interval, wherein the differential value is a difference between a write pointer and a read pointer of the FIFO buffer, and the second specific interval has a second upper limit value and a second lower limit value;

when the deviation value is larger than the second upper limit value, increasing the clock rate;

when the deviation value is less than the second lower limit value, decreasing the clock rate; and

when the deviation value falls within the second specific interval, maintaining the clock rate.

2. The clock rate control method according to claim 1 , further comprising:

when the usage falls within the first specific interval, maintaining the clock rate.

3. The clock rate control method according to claim 1 , wherein the first upper limit value is the half of packet buffer number of the FIFO buffer adding a first specific value, and the first lower limit value is the half of packet buffer number of the FIFO buffer subtracting a second specific value, wherein the first specific value and the second specific value are positive integers.

4. The clock rate control method according to claim 1 , wherein the second upper limit value is a positive integer, and the second lower limit value is a negative integer.

5. A clock rate controller, comprising:

a usage detection unit, electrically connected to a FIFO buffer of an electronic device, used to detect a usage of the FIFO buffer; and

a speed up/down determining unit, electrically connected to the usage detection unit and an internal device of the electronic device, used to detect whether the usage falls within a first specific interval, wherein the first specific interval has a first upper limit value and a first lower limit value;

a deviation value calculating unit, electrically connected to the FIFO buffer and the speed up/down determining unit, used to calculate a deviation value between a current differential value and a previous differential value, wherein the differential value is a difference between a write pointer and a read pointer of the FIFO buffer;

wherein when the usage is larger than the first upper limit value, the speed up/down determining unit increases a clock rate of the internal device of the electronic device; when the usage is less than the first lower limit value, the speed up/down determining unit decreases the clock rate;

wherein when the usage falls within the first specific interval, the speed up/down determining unit determines whether the deviation value falls within a second specific interval, wherein the second specific interval has a second upper limit value and a second lower limit value; when the deviation value is larger than the second upper limit value, the speed up/down determining unit increases the clock rate; when the deviation value is less than the second lower limit value, the speed up/down determining unit decreases the clock rate; when the deviation value falls within the second specific interval, the speed up/down determining unit maintains the clock rate.

6. The clock rate controller according to claim 5 , wherein when the usage falls within the first specific interval, the speed up/down determining unit maintains the clock rate.

7. The clock rate controller according to claim 5 , wherein the first upper limit value is the half of packet buffer number of the FIFO buffer adding a first specific value, and the first lower limit value is the half of packet buffer number of the FIFO buffer subtracting a second specific value, wherein the first specific value and the second specific value are positive integers.

8. The clock rate controller according to claim 5 , wherein the second upper limit value is a positive integer, and the second lower limit value is a negative integer.

9. An electronic device, used to connect a host, comprising:

a FIFO buffer, electrically connected to the host, used to store a plurality of packet from the host;

a clock rate controller, electrically connected to the FIFO buffer, used to determines whether a usage of the FIFO buffer falls within a first specific interval, wherein the first specific interval has a first upper limit value and a first lower limit value; and

an internal device, electrically connected to the clock rate controller and the FIFO buffer, used to process the packet from the FIFO buffer according to a clock rate;

wherein when the usage is larger than the first upper limit value, the clock rate controller increases the clock rate; when the usage is less than the first lower limit value, the clock rate controller decreases the clock rate;

wherein when the usage falls within the first specific interval, the clock rate controller maintains the clock rate;

wherein the clock rate controller determines whether a deviation value between a current differential value and a previous differential value falls within a second specific interval, wherein the differential value is a difference between a write pointer and a read pointer of the FIFO buffer, and the second specific interval has a second upper limit value and a second lower limit value; when the usage falls within the first specific interval, the speed up/down determining unit determines whether the deviation value falls within a second specific interval, wherein the second specific interval has a second upper limit value and a second lower limit value; when the deviation value is larger than the second upper limit value, the clock rate controller increases the clock rate; when the deviation value is less than the second lower limit value, the clock rate controller decreases the clock rate; when the deviation value falls within the second specific interval, the clock rate controller maintains the clock rate.

10. The electronic device according to claim 9 , wherein the clock rate controller comprises:

a usage detection unit, electrically connected to the FIFO buffer, used to detect the usage; and

a speed up/down determining unit, electrically connected to the usage detection unit and the internal device, used to detect whether the usage falls within the first specific interval;

wherein when the usage is larger than the first upper limit value, the speed up/down determining unit increases the clock rate; when the usage is less than the first lower limit value, the speed up/down determining unit decreases the clock rate.

11. The electronic device according to claim 10 , wherein when the usage falls within the first specific interval, the speed up/down determining unit maintains the clock rate.

12. The electronic device according to claim 10 , wherein the clock rate controller further comprising:

a deviation value calculating unit, electrically connected to the FIFO buffer and the speed up/down determining unit, used to calculate a deviation value between a current differential value and a previous differential value, wherein the differential value is a difference between a write pointer and a read pointer of the FIFO buffer;

wherein when the usage falls within the first specific interval, the speed up/down determining unit determines whether the deviation value falls within a second specific interval, wherein the second specific interval has a second upper limit value and a second lower limit value; when the deviation value is larger than the second upper limit value, the speed up/down determining unit increases the clock rate; when the deviation value is less than the second lower limit value, the speed up/down determining unit decreases the clock rate; when the deviation value falls within the second specific interval, the speed up/down determining unit maintains the clock rate.

13. The electronic device according to claim 12 , wherein the second upper limit value is a positive integer, and the second lower limit value is a negative integer.

14. The electronic device according to claim 10 , wherein the first upper limit value is the half of packet buffer number of the FIFO buffer adding a first specific value, and the first lower limit value is the half of packet buffer number of the FIFO buffer subtracting a second specific value, wherein the first specific value and the second specific value are positive integers.

15. The electronic device according to claim 9 , wherein the first upper limit value is the half of packet buffer number of the FIFO buffer adding a first specific value, and the first lower limit value is the half of packet buffer number of the FIFO buffer subtracting a second specific value, wherein the first specific value and the second specific value are positive integers.

16. The electronic device according to claim 6 , wherein the second upper limit value is a positive integer, and the second lower limit value is a negative integer.