IP Library Granted Patent US 8,908,745
Granted Patent B2
US 8,908,745 · App. 13/008,072 · Granted Dec 9, 2014

Analog continuous time matched pulse shaping transmitter and receiver filters

Inventors: Vladimir Pelekhaty (Baltimore, MD); Michael Y. Frankel (Baltimore, MD); Michael J. Wingrove (Kanata, CA)
Assignee: Ciena Corporation
H04L27/36H04L25/0384H03H17/0289
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Quick Facts
Patent No.
US 8,908,745
App. No.
13/008,072
Granted
Dec 9, 2014
Kind
B2
Abstract

The present invention provides a transmission system, including: a transmitter including a transmitter filter; a receiver including a receiver filter; and a communicative coupling between the transmitter and the receiver; wherein the transmitter filter and the receiver filter are matched for noise reduction, and wherein the combined responses of the transmitter filter and the receiver filter satisfy the Nyquist criteria. Optionally, the transmitter filter includes a pulse shaping quasi digital finite impulse response filter. Optionally, the receiver filter includes an inductor-capacitor ladder based filter.

Claims (32)

1. A circuit, comprising:

a transmitter filter comprising a quasi digital filter that utilizes digital data as inputs provided to a shift register buffer stage and clocked through the shift register buffer stage in a discrete-time manner and outputs of the shift register buffer stage that are continuous-time analog signals which are weighted and summed in an analog domain;

a receiver filter comprising an analog filter; and

a communicative coupling between the transmitter filter and the receiver filter;

wherein the transmitter filter and the receiver filter are matched for noise reduction, wherein the transmitter filter compensates for non-ideal filtering properties of the receiver filter by adjusting its taps, and wherein the combined responses of the transmitter filter and the receiver filter satisfy the Nyquist criteria;

wherein the transmitter filter comprises a pulse shaping quasi digital finite impulse response filter, wherein the transmitter filter is dynamically adaptable to compensate for optical channel distortion impairments; and

wherein the receiver filter comprises an inductor-capacitor ladder based filter, wherein only a single separate receiver filter is used per I and Q data streams prior to demodulation and decision slicing of a multi-level, multi-bit modulation formatted signal.

2. The circuit of claim 1 , wherein the pulse shaping quasi digital finite impulse response filter utilizes a combination of digital delays and analog coefficient control and tap summation.

3. The circuit of claim 1 , wherein the pulse shaping quasi digital finite impulse response filter is calibrated to compensate for residual manufacturing imperfections of both transmitter and receiver components.

4. The circuit of claim 1 , wherein the pulse shaping quasi digital finite impulse response filter and transmitter data processing are utilized to provide simultaneous pulse shaping and digital-to-analog conversion required for multi level, multi bit modulation formats.

5. The circuit of claim 1 , wherein the inductor-capacitor ladder based filter is implemented in one of CMOS and BiCMOS circuitry.

6. The circuit of claim 1 , wherein the transmitter filter and the receiver filter are selected and matched such that they provide optimized suppression of one or more of inter signal interference and inter channel interference.

7. A transmission system, comprising:

a transmitter comprising a transmitter filter comprising a quasi digital filter that utilizes digital data as inputs provided to a shift register buffer stage and clocked through the shift register buffer stage in a discrete-time manner and outputs of the shift register buffer stage that are continuous-time analog signals which are weighted and summed in an analog domain;

a receiver comprising a receiver filter comprising an analog filter; and

a communicative coupling between the transmitter and the receiver;

wherein the transmitter filter and the receiver filter are matched for noise reduction, wherein the transmitter filter compensates for non-ideal filtering properties of the receiver filter by adjusting its taps, and wherein the combined responses of the transmitter filter and the receiver filter satisfy the Nyquist criteria;

wherein the transmitter filter comprises a pulse shaping quasi digital finite impulse response filter, wherein the transmitter filter is dynamically adaptable to compensate for optical channel distortion impairments; and

wherein the receiver filter comprises an inductor-capacitor ladder based filter, wherein only a single separate receiver filter is used per I and Q data streams prior to demodulation and decision slicing of a multi-level, multi-bit modulation formatted signal.

8. The transmission system of claim 7 , wherein the pulse shaping quasi digital finite impulse response filter utilizes a combination of digital delays and analog coefficient control and tap summation.

9. The transmission system of claim 7 , wherein the pulse shaping quasi digital finite impulse response filter is calibrated to compensate for residual manufacturing imperfections of both the transmitter and the receiver.

10. The transmission system of claim 7 , wherein the pulse shaping quasi digital finite impulse response filter and transmitter data processing are utilized to provide simultaneous pulse shaping and digital-to-analog conversion required for multi level, multi bit modulation formats.

11. The transmission system of claim 7 , wherein the inductor-capacitor ladder based filter is implemented in one of CMOS and BiCMOS circuitry.

12. The transmission system of claim 7 , wherein the transmitter filter and the receiver filter are selected and matched such that they provide optimized suppression of one or more of inter symbol interference and inter channel interference.

13. A transmission method, comprising:

at a transmitter, filtering a signal utilizing a transmitter filter comprising a quasi digital filter that utilizes digital data as inputs provided to a shift register buffer stage and clocked through the shift register buffer stage in a discrete-time manner and outputs of the shift register buffer stage that are continuous-time analog signals which are weighted and summed in an analog domain;

transmitting the signal from the transmitter to the receiver utilizing a communicative coupling; and

at a receiver, filtering the signal utilizing a receiver filter comprising an analog filter;

wherein the transmitter filter and the receiver filter are matched for noise reduction, wherein the transmitter filter compensates for non-ideal filtering properties of the receiver filter by adjusting its taps, and wherein the combined responses of the transmitter filter and the receiver filter satisfy the Nyquist criteria;

wherein the transmitter filter comprises a pulse shaping quasi digital finite impulse response filter, wherein the transmitter filter is dynamically adaptable to compensate for optical channel distortion impairments; and

wherein the receiver filter comprises an inductor-capacitor ladder based filter, wherein only a single separate receiver filter is used per I and Q data streams prior to demodulation and decision slicing of a multi-level, multi-bit modulation formatted signal.

14. The transmission method of claim 13 , wherein the transmitter filter and the receiver filter are selected and matched such that they provide optimized suppression of one or more of inter signal interference and inter channel interference.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2011
From: PELEKHATY, VLADIMIR; FRANKEL, MICHAEL Y.; WINGROVE, MICHAEL J.
To: CIENA CORPORATION
Reel/Frame 025650/0850 →
Continuity (1)
Related Publication 20120183092A1 · Jul 19, 2012