IP Library Granted Patent US 8,912,604
Granted Patent B2
US 8,912,604 · App. 13/800,556 · Granted Dec 16, 2014

Semiconductor device having buried bit lines and method for fabricating the same

Inventors: Ju-Hyun Myung (Gyeonggi-do, KR); Eui-Seong Hwang (Gyeonggi-do, KR); Eun-Shil Park (Gyeonggi-do, KR); Tae-Yoon Kim (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L27/10829H01L29/7827H01L27/10885H01L27/10876H01L29/165H01L29/45H01L29/66666H01L29/41741
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Quick Facts
Patent No.
US 8,912,604
App. No.
13/800,556
Granted
Dec 16, 2014
Kind
B2
Abstract

A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.

Claims (26)

1. A semiconductor device comprising:

body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls;

buried bit lines, buried in the recessed sidewalls; and a barrier layer, interposed between each of the buried bit lines and each of the body lines corresponding thereto.

2. The semiconductor device according to claim 1 , wherein each of the buried bit lines comprises a metal silicide and the barrier layer comprises germanium.

3. The semiconductor device according to claim 2 , wherein the barrier layer includes silicon germanium.

4. The semiconductor device according to claim 2 , wherein a content of germanium in the barrier layer is at least approximately 30%.

5. The semiconductor device according to claim 2 , wherein the metal silicide comprises a cobalt silicide.

6. A semiconductor device comprising:

a plurality of active regions separated from one another;

a plurality of first trenches defined in a substrate, wherein the plurality of active regions are separated from one another by the plurality of first trenches;

supporters filled in the plurality of first trenches;

second trenches, each separating each of the plurality of active regions, and each having recessed sidewalls that face each other;

a pair of separated buried bit lines, formed in each of the second trenches, and including a metal silicide; and

a barrier layer, interposed between the pair of separated buried bit lines and each of the second trenches, and containing germanium.

7. The semiconductor device according to claim 6 , wherein each of the plurality of active regions comprises:

a body formed over the substrate;

a pair of body lines, separated by each of the second trenches over the body, and having the recessed sidewalls; and

a plurality of pillars formed over each of the pair of body lines.

8. The semiconductor device according to claim 6 ,

wherein the plurality of pillars includes channel regions for vertical channel transistors, and

wherein the semiconductor device further comprises:

storages connected to the plurality of pillars.

9. The semiconductor device according to claim 6 , wherein the supporters comprise a dielectric material.

10. The semiconductor device according to claim 6 , wherein the barrier layer comprises silicon germanium.

11. The semiconductor device according to claim 6 , wherein a content of germanium in the barrier layer is at least approximately 30%.

12. The semiconductor device according to claim 6 , wherein the metal silicide comprises a cobalt silicide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2013
From: MYUNG, JU-HYUN; HWANG, EUI-SEONG; PARK, EUN-SHIL; KIM, TAE-YOON
To: SK HYNIX INC.
Reel/Frame 029986/0846 →
Priority Claims (1)
KR 10-2012-0094372 · Aug 28, 2012 · national
Continuity (1)
Related Publication 20140061745A1 · Mar 6, 2014