Counter-based entry invalidation for metadata previous write queue
View Patent ↗Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.
1. A computer system for counter-based entry invalidation for a metadata previous write queue (PWQ), the system comprising:
a processor;
a pipeline associated with the processor; and
a metadata PWQ, the system configured to perform a method comprising:
writing, by the processor, an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline;
setting a valid tag associated with the entry in the metadata PWQ to valid;
initializing a counter to zero;
incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold; and
setting the valid tag to invalid based on the counter being equal to the threshold.
2. The computer system of claim 1 , wherein the metadata PWQ comprises a plurality of entries, each of the plurality of entries having an associated respective valid tag, and wherein setting the valid tag to invalid further comprises setting each of the plurality of valid tags associated with the plurality of entries to invalid.
3. The computer system of claim 1 , wherein the metadata PWQ comprises a plurality of entries, and further comprising a plurality of counters, each of the plurality of counters being associated with a respective entry of the plurality of entries.
4. The computer system of claim 3 , wherein initializing a counter to zero comprises initializing a respective counter of the plurality of counters associated with the entry to zero based on writing an address into the entry.
5. The computer system of claim 3 , further comprising incrementing each of the plurality of counters simultaneously based on the count signal from the pipeline.
6. The computer system of claim 3 , further comprising a plurality of thresholds, each threshold being associated with a respective counter of the plurality of counters, and wherein determining whether the counter is equal to the threshold comprises determining whether the counter is equal to counter's respective threshold.
7. The computer system of claim 6 , wherein a value of a threshold is determined based on one of a number of operations associated with the address that are in the pipeline at the time of writing the address into the entry in the metadata PWQ, and a total number of operations in the pipeline at the time of writing the address into the entry in the metadata PWQ.
8. The computer system of claim 1 , further comprising:
receiving an address and an instance of metadata for writing into a metadata store associated with the metadata PWQ;
determining whether a matching entry for the address exists in the metadata PWQ;
determining whether a valid tag in the matching entry is set to valid based on determining that the matching entry for the address exists in the metadata PWQ; and
avoiding writing the address and the instance of metadata into the metadata store based on determining that the valid tag in the matching entry is set to valid.